Electron-beam fabrication of submicron gates for GaAs FET's

High‐performance GaAs FET’s with nominal gate lengths of 0.5, 0.75, and 1.0 μm have been fabricated with electron‐beam‐lithography techniques. A hybrid process was developed which only required e‐beam definition of the critical gate level and was otherwise compatible with the fabrication process developed for conventional optically defined gates. The source–drain metallization mask was modified to include alignment marks for the gate level and the source–drain metallization was augmented to give marks after alloying with acceptable secondary electron contrast against the GaAs background: ±2000 A registration was routinely achieved over the 80×80 mil2 field. A test pattern which could be examined optically with rapid turnaround to determine the proper exposures for the various gate lengths was employed. The pattern evaluation was confirmed by resist exposure studies in conjunction with SEM examination. Evaluation of the test pattern together with corrections for the GaAs substrate backscatter and proximity effect allowed control of the gate lengths to ±10% over the entire slice. The gates were tapered at the mesa edge to prevent constriction of the resist over the step. The resist used was polymethyl methacrylate (PMMA) with a nominal thickness of 7500 A and the developed pattern served as the lift‐off mask for 4000–5000 A of aluminum gate metallization. The nominal slice size used for these runs was slightly greater than 1 cm2 (420×420 mil2) and up to 588 devices were patterned in a single pumpdown. The exposure time required per slice, including stage step and alignment, was six minutes. Both small signal and power GaAs FET’s have been fabricated with e‐beam defined gates. Small signal devices with 0.75μm gate lengths had 2.0 dB minimum noise figures with 10 dB gain at 9 GHz. Power devices with 4800‐μm total gate width and 1‐μm gate length had up to 4.1 W output power at 8 GHz with 4 dB gain.