Review on Clock Gating Techniques

this is an era of hand held devices like cellular mobile phones, personal digital assistants and many more. This is possible because of microprocessors embedded in these devices. These devices must operate at high speeds but at the same time must survive long standby time. So low power high speed processors are the need of the hour, one such method for reducing dynamic power consumption is clock gating. This paper reviews various clock gating techniques available in literature. Keywords— Clock gating, dynamic power consumption, FPGA

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