Implementation of FPGA-based real time novel chaotic oscillator

Currently, chaotic systems and chaos-based applications are commonly used in the engineering fields. One of the main structures used in these applications is the chaos-based signal generators. Chaotic signal generators have an important role, particularly in chaotic communication and cryptology. In this study, the Pehlivan-Wei chaotic system, which is a recently developed chaotic system, has been implemented with FPGA using three distinct algorithms (the Euler, Heun, and RK4) for the first time in literature. Numerical and HDL approaches are implemented by these three algorithms to compare the performance of each model for use in chaotic generators. In addition, the Lyapunov exponents and phase portraits of the system have been extracted for chaos analysis. RMSE analysis has been conducted on the chaotic generators, which are modeled using the Euler, Heun, and RK4 algorithms in order to observe error rates of each numerical algorithm in a comparative aspect. The performance of new chaotic system with various data sets has been analyzed. The operation frequency of the chaotic oscillators synthesized and tested for the Virtex-6 FPGA chip has been able to reach up to 463.688 MHz and the chaotic system has been able to calculate 300,000 data sets in 0.0284 s. However, PC-based algorithm having highest performance score can calculate 300,000 data sets in a period of 75.363 s. A comparison study has been performed on the performance of the FPGA-based and PC-based solutions to evaluate each approach.

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