Fast estimation of RL-loaded microelectronic interconnections delay for the signal integrity prediction

This article presents a modelling method of the signal delays induced by microelectronic interconnections regarding RL impedance load. The method proposed is based on the RLC model of the transmission lines (TL) extracted from the equivalent S parameters. Formulation for estimating the interconnection propagation delay is established according to the behaviour of the TL unit step responses. The second order model is validated with a microstrip interconnect prototype with simulations and measurements in frequency and time domains. The developed propagation delay model was validated with SPICE computations. For that, a transient simulation was performed by considering input signals corresponding to high-speed data of some Gbits/s. Then, accurate results were found for interconnections with different lengths in order of millimetre and also by varying the load values. It was shown that the computed 50% propagation delays present of relative errors about 5%. Copyright © 2011 John Wiley & Sons, Ltd.

[1]  A. Ciccomancini Scogna,et al.  Efficient methodologies to study the signal integrity of multi Gb/s interconnects and full system EMC , 2009, 2009 IEEE International Symposium on Electromagnetic Compatibility.

[2]  Blaise Ravelo,et al.  TRANSIENT RESPONSE CHARACTERIZATION OF THE HIGH-SPEED INTERCONNECTION RLCG-MODEL FOR THE SIGNAL INTEGRITY ANALYSIS , 2011 .

[3]  W. Heinrich,et al.  Model of thin-film microstrip line for circuit design , 2001 .

[4]  Yang Yintang,et al.  Optimal cascade lumped model of deep submicron on-chip interconnect with distributed parameters , 2005 .

[5]  Víctor H. Champac,et al.  Built-In Sensor for Signal Integrity Faults in Digital Interconnect Signals , 2010, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[6]  Jun-Fa Mao,et al.  High-speed Clock Tree Simulation Method Based on Moment Matching , 2005 .

[7]  Andrew B. Kahng,et al.  An analytical delay model for RLC interconnects , 1997, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[8]  Blaise Ravelo,et al.  A New Technique of Interconnect Effects Equalization by Using Negative Group Delay Active Circuits , 2010 .

[9]  Thomas Y. Hsiang,et al.  Extraction of Subterahertz Transmission-line Parameters of Coplanar Waveguides , 2007 .

[10]  Eby G. Friedman,et al.  Repeater design to reduce delay and power in resistive interconnect , 1998 .

[11]  Anestis Dounavis,et al.  Efficient passive circuit models for distributed networks with frequency-dependent parameters , 2000 .

[12]  W. Bandurski,et al.  Effect of inductance on interconnect propagation delay in VLSI circuits , 2004, Proceedings. 8th IEEE Workshop on Signal Propagation on Interconnects.

[13]  W. C. Elmore.  The Transient Response of Damped Linear Networks with Particular Regard to Wideband Amplifiers , 1948 .

[14]  Yehea I. Ismail,et al.  Effects of inductance on the propagation delay and repeater insertion in VLSI circuits , 2000, IEEE Trans. Very Large Scale Integr. Syst..

[15]  Jason Cong,et al.  Performance optimization of VLSI interconnect layout , 1996, Integr..

[16]  J. L. Prince,et al.  A new discrete transmission line model for passive model order reduction and macromodeling of high-speed interconnections , 1999 .

[17]  Hsien-Hsin S. Lee,et al.  Pragmatic Integration of an SRAM Row Cache in Heterogeneous 3-D DRAM Architecture Using TSV , 2013, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[18]  Gerard V. Kopcsay,et al.  High-Speed Signal Propagation on Lossy Transmission Lines , 1990, IBM J. Res. Dev..

[19]  Chandramouli V. Kashyap,et al.  Closed-form expressions for extending step delay and slew metrics to ramp inputs for RC trees , 2004, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[20]  Yun Bai,et al.  Optimization of Driver Preemphasis for On-Chip Interconnects , 2009, IEEE Transactions on Circuits and Systems I: Regular Papers.

[21]  Paul Ampadu,et al.  Self-Adaptive System for Addressing Permanent Errors in On-Chip Interconnects , 2010, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.