Investigation of 6T SRAM memory circuit using high-k dielectrics based nano scale junctionless transistor

Abstract In this paper the Dual Metal Surround Gate Junctionless Transistor (DMSGJLT) has been implemented with various high-k dielectric. The leakage current in the device is analysed in detail by obtaining the band structure for different high-k dielectric material. It is noticed that with increasing dielectric constant the device provides more resistance for the direct tunnelling of electron in off state. The gate oxide capacitance also shows 0.1 μF improvement with Hafnium Oxide (HfO 2 ) than Silicon Oxide (SiO 2 ). This paved the way for a better memory application when high-k dielectric is used. The Six Transistor (6T) Static Random Access Memory (SRAM) circuit implemented shows 41.4% improvement in read noise margin for HfO 2 than SiO 2 . It also shows 37.49% improvement in write noise margin and 30.16% improvement in hold noise margin for HfO 2 than SiO 2 .

[1]  K. Ishibashi,et al.  A 65-nm SoC Embedded 6T-SRAM Designed for Manufacturability With Read and Write Operation Stabilizing Circuits , 2007, IEEE Journal of Solid-State Circuits.

[2]  Subhasis Haldar,et al.  An analytical drain current model for dual material engineered cylindrical/surrounded gate MOSFET , 2012, Microelectron. J..

[3]  A.A. Orouji,et al.  Dual material gate oxide stack symmetric double gate MOSFET: Improving short channel effects of nanoscale double gate MOSFET , 2008, 2008 11th International Biennial Baltic Electronics Conference.

[4]  J. Robertson.  High dielectric constant oxides , 2004 .

[5]  R. Xu,et al.  Junctionless MOSFETs with laterally graded-doping channel for analog/RF applications , 2013 .

[6]  Ken K. Chin,et al.  Dual-material gate (DMG) field effect transistor , 1999 .

[7]  Neeta Sharma.  COMPARATIVE ANALYSIS OF POWER REDUCTION IN SRAM 6T AND 4T , 2015 .

[8]  J. Sallese,et al.  Charge-Based Modeling of Junctionless Double-Gate Field-Effect Transistors , 2011, IEEE Transactions on Electron Devices.

[9]  D. Nirmal,et al.  Implementation of nanoscale circuits using dual metal gate engineered nanowire MOSFET with high-k dielectrics for low power applications , 2016 .

[10]  V. Rao,et al.  Impact of High-$k$ Gate Dielectrics on the Device and Circuit Performance of Nanoscale FinFETs , 2007, IEEE Electron Device Letters.

[11]  Xinnan Lin,et al.  Suppression of tunneling leakage current in junctionless nanowire transistors , 2013 .

[12]  K. Roy,et al.  Device-Optimization Technique for Robust and Low-Power FinFET SRAM Design in NanoScale Era , 2007, IEEE Transactions on Electron Devices.

[13]  Pinaki Mazumder,et al.  A robust 12T SRAM cell with improved write margin for ultra-low power applications in 40 nm CMOS , 2017, Integr..

[14]  M. Saxena,et al.  Dual Material Double-Layer Gate Stack SON MOSFET: A Novel Architecture for Enhanced Analog Performance—Part I: Impact of Gate Metal Workfunction Engineering , 2008, IEEE Transactions on Electron Devices.

[15]  D. Nirmal,et al.  A review of InP/InAlAs/InGaAs based transistors for high frequency applications , 2015 .

[16]  C. Pacha,et al.  Layout options for stability tuning of SRAM cells in multi-gate-FET technologies , 2007, ESSCIRC 2007 - 33rd European Solid-State Circuits Conference.

[17]  O. Faynot,et al.  Scaling of Trigate Junctionless Nanowire MOSFET With Gate Length Down to 13 nm , 2012, IEEE Electron Device Letters.

[18]  D. Nirmal,et al.  A New Drain Current Model for a Dual Metal Junctionless Transistor for Enhanced Digital Circuit Performance , 2016, IEEE Transactions on Electron Devices.

[19]  H. Fujiwara,et al.  An Area-Conscious Low-Voltage-Oriented 8T-SRAM Design under DVS Environment , 2007, 2007 IEEE Symposium on VLSI Circuits.

[20]  Shengqi Yang,et al.  A Junctionless Nanowire Transistor With a Dual-Material Gate , 2012, IEEE Transactions on Electron Devices.

[21]  E. Suzuki,et al.  Enhancing SRAM cell performance by using independent double-gate FinFET , 2008, 2008 IEEE International Electron Devices Meeting.

[22]  Performance Analysis of Junctionless Transistors Based on Monte Carlo Simulation , 2012 .

[23]  P. Vijayakumar,et al.  Subthreshold performance of gate engineered FinFET devices and circuit with high-k dielectrics , 2013, Microelectron. Reliab..

[24]  Chi-Woo Lee,et al.  Nanowire transistors without junctions. , 2010, Nature nanotechnology.

[25]  Deepak Aggarwal,et al.  A Comparative Study of 6T, 8T and 9T Sram Cell , 2012 .

[26]  D. Nirmal,et al.  Subthreshold analysis of nanoscale FinFETs for ultra low power application using high-k materials , 2013 .

[27]  A. Gnudi,et al.  Theory of the Junctionless Nanowire FET , 2011, IEEE Transactions on Electron Devices.

[28]  Ming-Hsien Tu,et al.  40 nm Bit-Interleaving 12T Subthreshold SRAM With Data-Aware Write-Assist , 2014, IEEE Transactions on Circuits and Systems I: Regular Papers.

[29]  Horng-Chih Lin,et al.  Characteristics of n-Type Junctionless Poly-Si Thin-Film Transistors With an Ultrathin Channel , 2012, IEEE Electron Device Letters.

[30]  A. Bouazra,et al.  Current Tunnelling in MOS Devices withAl2O3/SiO2 Gate Dielectric , 2008 .

[31]  S. Ganguly,et al.  Effect of Band-to-Band Tunneling on Junctionless Transistors , 2012, IEEE Transactions on Electron Devices.