CNFET based ternary magnitude comparator

Ternary logic is a promising alternative to conventional binary logic, since it is possible to achieve simplicity and energy efficiency due to the reduced circuit overhead. In this paper, a ternary magnitude comparator design based on Carbon Nanotube Field Effect Transistors (CNFETs) is presented. This design eliminates the usage of complex ternary decoder which is a part of existing designs. Elimination of decoder results in reduction of delay and power. Simulations of proposed and existing designs are done on HSPICE and results proves that the proposed 1-bit comparator consumes 81% less power and shows delay advantage of 41.6% compared to existing design. Further a methodology to extend the 1-bit comparator design to n-bit comparator design is also presented.

[1]  Andreas Antoniou,et al.  Low power dissipation MOS ternary logic family , 1984 .

[2]  Masao Mukaidono.  Regular Ternary Logic Functions—Ternary Logic Functions Suitable for Treating Ambiguity , 1986, IEEE Transactions on Computers.

[3]  Li Wei,et al.  (n,m) Selectivity of single-walled carbon nanotubes by different carbon precursors on Co-Mo catalysts. , 2007, Journal of the American Chemical Society.

[4]  Fabrizio Lombardi,et al.  Device Model for Ballistic CNFETs Using the First Conducting Band , 2008, IEEE Design & Test of Computers.

[5]  H. Wong,et al.  A Compact SPICE Model for Carbon-Nanotube Field-Effect Transistors Including Nonidealities and Its Application—Part I: Model of the Intrinsic Channel Region , 2007, IEEE Transactions on Electron Devices.

[6]  Yong-Bin Kim,et al.  CNTFET-Based Design of Ternary Logic Gates and Arithmetic Circuits , 2011, IEEE Transactions on Nanotechnology.

[7]  Jie Deng,et al.  A Compact SPICE Model for Carbon-Nanotube Field-Effect Transistors Including Nonidealities and Its Application—Part II: Full Device Model and Circuit Performance Benchmarking , 2007, IEEE Transactions on Electron Devices.

[8]  V. T. Ingole,et al.  Design And Implementation Of 2 Bit Ternary ALU Slice , 2005 .

[9]  Yutaka Ohno,et al.  Chirality assignment of individual single-walled carbon nanotubes in carbon nanotube field-effect transistors by micro-photocurrent spectroscopy , 2004 .

[10]  David A. Rich,et al.  A Survey of Multivalued Memories , 1986, IEEE Transactions on Computers.

[11]  Jörg Appenzeller,et al.  Carbon Nanotubes for High-Performance Electronics—Progress and Prospect , 2008, Proceedings of the IEEE.

[12]  H. T. Mouftah,et al.  Depletion/enhancement CMOS for a lower power family of three-valued logic circuits , 1985 .

[13]  T. Nakamura,et al.  Realization of quaternary logic circuits by n-channel MOS devices , 1986 .

[14]  F. Lombardi,et al.  A novel CNTFET-based ternary logic gate design , 2009, 2009 52nd IEEE International Midwest Symposium on Circuits and Systems.

[15]  K. Roy,et al.  Carbon-nanotube-based voltage-mode multiple-valued logic design , 2005, IEEE Transactions on Nanotechnology.

[16]  David Li,et al.  A Low-Power High-Performance Single-Cycle Tree-Based 64-Bit Binary Comparator , 2012, IEEE Transactions on Circuits and Systems II: Express Briefs.