DART: a dynamically reconfigurable architecture dealing with future mobile telecommunications constr

In addition to the high performance requirements inherent to multimedia processings or to W-CDMA, future generation mobile telecommunications brings new constraints to the semiconductor design world. In fact, to support these processings, a system will have to be very flexible, in order to support the various algorithms allowed by the norm and the addition of new services, while keeping an energy consumption level compatible with the portability notion of this system. In order to associate high performances and low energy consumption in a flexible system, we developed a dynamically reconfigurable architecture called DART. The aim of this paper is to present this architecture and to estimate its level of performance and its adequacy with future generation mobile telecommunication systems.

[1]  Ramjee Prasad,et al.  Wideband CDMA For Third Generation Mobile Communications: Universal Personal Communications , 1998 .

[2]  Ramjee Prasad,et al.  Wideband CDMA for third generation mobile communications , 1998 .

[3]  Mark Horowitz,et al.  Energy dissipation in general purpose microprocessors , 1996, IEEE J. Solid State Circuits.

[4]  Carl Ebeling,et al.  Architecture design of reconfigurable pipelined datapaths , 1999, Proceedings 20th Anniversary Conference on Advanced Research in VLSI.

[5]  Bijan Jabbari,et al.  Spreading codes for direct sequence CDMA and wideband CDMA cellular networks , 1998, IEEE Commun. Mag..

[6]  A Low-Energy Heterogeneous Reconfigurable DSP IC 1 , 1999 .

[7]  Joseph Cavanagh,et al.  Digital Computer Arithmetic , 1983 .

[8]  Reiner W. Hartenstein,et al.  A decade of reconfigurable computing: a visionary retrospective , 2001, Proceedings Design, Automation and Test in Europe. Conference and Exhibition 2001.

[9]  J. Fridman.  Sub-word parallelism in digital signal processing , 2000 .

[10]  John Wawrzynek,et al.  Garp: a MIPS processor with a reconfigurable coprocessor , 1997, Proceedings. The 5th Annual IEEE Symposium on Field-Programmable Custom Computing Machines Cat. No.97TB100186).

[11]  Xinan Tang,et al.  A Compiler Directed Approach to Hiding Configuration Latency in Chameleon Processors , 2000, FPL.

[12]  Chris Phillips.  Wireless Base Station Design Using a Reconfigurable Communications Processor , 2000, FPL.

[13]  Low Energy Field-Programmable Gate Array , .

[14]  Jan M. Rabaey,et al.  Ultra-low-power domain-specific multimedia processors , 1996, VLSI Signal Processing, IX.

[15]  Masami Akamine,et al.  CELP speech coding based on an adaptive pulse position codebook , 1999, 1999 IEEE International Conference on Acoustics, Speech, and Signal Processing. Proceedings. ICASSP99 (Cat. No.99CH36258).

[16]  Jan M. Rabaey,et al.  Interconnect architecture exploration for low-energy reconfigurable single-chip DSPs , 1999, Proceedings. IEEE Computer Society Workshop on VLSI '99. System Design: Towards System-on-a-Chip Paradigm.

[17]  Joseph J. F. Cavanagh.  Digital Computer Arithmetic: Design And Implementation , 1984 .

[18]  Seth Copen Goldstein,et al.  PipeRench: A Reconfigurable Architecture and Compiler , 2000, Computer.

[19]  L. Hanzo,et al.  Interactive cellular and cordless video telephony: State-of-the-art system design principles and expected performance , 2000, Proceedings of the IEEE.

[20]  Maya Gokhale,et al.  The NAPA adaptive processing architecture , 1998, Proceedings. IEEE Symposium on FPGAs for Custom Computing Machines (Cat. No.98TB100251).

[21]  Jan M. Rabaey,et al.  Reconfigurable processing: the solution to low-power programmable DSP , 1997, 1997 IEEE International Conference on Acoustics, Speech, and Signal Processing.

[22]  Olivier Sentieys,et al.  Fast Power Estimation at the architectural Level , 2000 .