A novel bulk-input low voltage and low power four quadrant analog multiplier in weak inversion

A new four quadrant voltage mode bulk input analog multiplier is presented .The proposed multiplier is designed to operate in weak inversion. Multiplication is done by driving the bulk terminals of the MOS devices which offers linear dynamic range of ±80 mV. The simulation shows, it has a linearity error of 5.6 %, THD of nearly 5 % and −3 dB band width of 221 kHz. Total power consumption is very low i.e. 714 nW. The circuit operates at a supply voltage of 0.5 V and is designed using 180 nm CMOS technology. It is suitable for low power bioelectronics and neural applications.

[1]  Christian Enz,et al.  MOS transistor modeling for low-voltage and low-power analog IC design , 1997 .

[2]  A. Pesavento,et al.  A wide linear range four quadrant multiplier in subthreshold CMOS , 1999, ISCAS'99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems VLSI (Cat. No.99CH36349).

[3]  Andreas G. Andreou,et al.  Current-mode subthreshold MOS circuits for analog VLSI neural systems , 1991, IEEE Trans. Neural Networks.

[4]  James J. Clark,et al.  A four-quadrant CMOS analog multiplier for analog neural networks , 1994, IEEE J. Solid State Circuits.

[5]  Emmanuel M. Drakakis,et al.  Harmonic vs. geometric mean Sinh integrators in weak inversion CMOS , 2008, 2008 IEEE International Symposium on Circuits and Systems.

[6]  Cheng-Chieh Chang,et al.  CMOS subthreshold four-quadrant multiplier based on unbalanced source-coupled pairs , 1995 .

[7]  F. Montecchi,et al.  Low voltage low power CMOS four-quadrant analog multiplier for neural network applications , 1996, 1996 IEEE International Symposium on Circuits and Systems. Circuits and Systems Connecting the World. ISCAS 96.

[8]  Eitake Ibaragi,et al.  A CMOS Analog Multiplier Free from Mobility Reduction and Body Effect , 1999 .

[9]  J. Fellrath,et al.  CMOS analog integrated circuits based on weak inversion operations , 1977 .

[10]  Zheng Li,et al.  A low-power CMOS analog multiplier , 2006, IEEE Transactions on Circuits and Systems II: Express Briefs.

[11]  Tzuen-Hsi Huang,et al.  Dependence of current match on back-gate bias in weakly inverted MOS transistors and its modeling , 1996 .

[12]  Y. Tsividis.  Operation and modeling of the MOS transistor , 1987 .

[13]  M. Valle,et al.  A novel current-mode very low power analog CMOS four quadrant multiplier , 2005, Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005..

[14]  R. R. Spencer.  Analog implementations of artificial neural networks , 1991, 1991., IEEE International Sympoisum on Circuits and Systems.

[15]  Shen-Iuan Liu,et al.  Design of a CMOS low-power and low-voltage four-quadrant analog multiplier , 2010 .

[16]  J.N. Babanezhad,et al.  A 20-V four-quadrant CMOS analog multiplier , 1985, IEEE Journal of Solid-State Circuits.

[17]  A.H.M. van Roermund,et al.  Translinear sin(x)-circuit in MOS technology using the back gate , 1995, ESSCIRC '95: Twenty-first European Solid-State Circuits Conference.

[18]  D. Coue,et al.  A four-quadrant subthreshold mode multiplier for analog neural-network applications , 1996, IEEE Trans. Neural Networks.

[19]  Eric A. Vittoz.  The Design of High-Performance Analog Circuits on Digital CMOS Chips , 1985 .

[20]  Grzegorz Blakiewicz.  Analog multiplier for a low-power integrated image sensor , 2009, 2009 MIXDES-16th International Conference Mixed Design of Integrated Circuits & Systems.

[21]  M. van de Gevel,et al.  Simple low-voltage weak inversion MOS 1/x circuit , 1994 .

[22]  Zheng Tang,et al.  Four-quadrant CMOS current-mode multiplier independent of device parameters , 2000 .

[23]  Barrie Gilbert,et al.  A precise four-quadrant multiplier with subnanosecond response , 1968, IEEE Solid-State Circuits Newsletter.

[24]  Abdollah Khoei,et al.  A new high speed and low power four-quadrant CMOS analog multiplier in current mode , 2009 .