A 12-bit, 2.5-bit/Phase Column-Parallel Cyclic ADC

A 12-bit, 1.67-MS/s, two-stage cyclic ADC, using a 1.5-bit algorithm in a 2.5-bit framework is proposed in this brief. The number of accurate comparators is reduced to half as compared with the conventional 2.5-bit stage, which reduces the power consumption. Furthermore, the pipelined operation of the two stages reduces the total number of clock-cycles, which improves the conversion rate. The proposed ADC is designed and fabricated in a standard 180-nm CMOS technology. The obtained differential nonlinearity and integral nonlinearity are +0.5/−0.5 LSB and +0.8/−0.9 LSB, respectively. The ADC consumes 435-<inline-formula> <tex-math notation="LaTeX">$\mu \text{W}$ </tex-math></inline-formula> of power and occupies an area of 0.045 mm<sup>2</sup>. The postlayout simulations of ADC designed in a column-pitch of 5.6 <inline-formula> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> show that it is suitable for column-parallel readout in CMOS image sensors.

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