Clock buffer polarity assignment considering capacitive load
暂无分享,去创建一个
[1] Charlie Chung-Ping Chen,et al. Fast and exact simultaneous gate and wire sizing by Lagrangian relaxation , 1998, ICCAD.
[2] Jiang Hu,et al. Clock Buffer Polarity Assignment for Power Noise Reduction , 2006, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[3] Kwang-Ting Cheng,et al. Electronic Design Automation: Synthesis, Verification, and Test , 2009 .
[4] Cristopher Moore,et al. Computational Complexity and Statistical Physics , 2006, Santa Fe Institute Studies in the Sciences of Complexity.
[5] Taewhan Kim,et al. Clock buffer polarity assignment combined with clock tree generation for power/ground noise minimization , 2008, 2008 IEEE/ACM International Conference on Computer-Aided Design.
[6] Thomas H. Cormen,et al. Introduction to algorithms [2nd ed.] , 2001 .
[7] TingTing Hwang,et al. Skew aware polarity assignment in clock tree , 2007, ICCAD.
[8] R. K. Shyamasundar,et al. Introduction to algorithms , 1996 .
[9] Taewhan Kim,et al. Simultaneous clock buffer sizing and polarity assignment for power/ground noise minimization , 2009, 2009 46th ACM/IEEE Design Automation Conference.
[10] TingTing Hwang,et al. Skew aware polarity assignment in clock tree , 2007, ICCAD 2007.
[11] Shih-Hsu Huang,et al. Minimizing peak current via opposite-phase clock tree , 2005, Proceedings. 42nd Design Automation Conference, 2005..
[12] Jan M. Rabaey,et al. Digital Integrated Circuits: A Design Perspective , 1995 .