A Genetic Representation for Evolutionary Fault Recovery in Virtex FPGAs

Most evolutionary approaches to fault recovery in FPGAs focus on evolving alternative logic configurations as opposed to evolving the intra-cell routing. Since the majority of transistors in a typical FPGA are dedicated to interconnect, nearly 80% according to one estimate, evolutionary fault-recovery systems should benefit by accommodating routing. In this paper, we propose an evolutionary fault-recovery system employing a genetic representation that takes into account both logic and routing configurations. Experiments were run using a software model of the Xilinx Virtex FPGA. We report that using four Virtex combinational logic blocks, we were able to evolve a 100% accurate quadrature decoder finite state machine in the presence of a stuck-at-zero fault.

[1]  Gunnar Tufte,et al.  Bridging the genotype-phenotype mapping for digital FPGAs , 2001, Proceedings Third NASA/DoD Workshop on Evolvable Hardware. EH-2001.

[2]  Delon Levi,et al.  JBits: Java based interface for reconfigurable computing , 1999 .

[3]  Sverre Vigander.  Evolutionary Fault Repair of Electronics in Space Applications , 2001 .

[4]  Julian Francis Miller,et al.  Evolving messy gates for fault tolerance: some preliminary findings , 2001, Proceedings Third NASA/DoD Workshop on Evolvable Hardware. EH-2001.

[5]  B. E. Wells,et al.  On the use of distributed reconfigurable hardware in launch control avionics , 2001, 20th DASC. 20th Digital Avionics Systems Conference (Cat. No.01CH37219).

[6]  Steven A. Guccione,et al.  GeneticFPGA: evolving stable circuits on mainstream FPGA devices , 1999, Proceedings of the First NASA/DoD Workshop on Evolvable Hardware.

[7]  Richard B. Katz,et al.  Report of the Odyssey FPGA Independent Assessment Team , 2001 .

[8]  Adrian Stoica,et al.  Fault-tolerant evolvable hardware using field-programmable transistor arrays , 2000, IEEE Trans. Reliab..

[9]  Jason D. Lohn,et al.  A comparison of dynamic fitness schedules for evolutionary design of amplifiers , 1999, Proceedings of the First NASA/DoD Workshop on Evolvable Hardware.

[10]  Mehdi Baradaran Tahoori,et al.  Fault grading FPGA interconnect test configurations , 2002, Proceedings. International Test Conference.

[11]  Andy M. Tyrrell,et al.  Evolved fault tolerance in evolvable hardware , 2002, Proceedings of the 2002 Congress on Evolutionary Computation. CEC'02 (Cat. No.02TH8600).

[12]  Adrian Thompson.  Evolving fault tolerant systems , 1995 .