Design for reuse of elliptic curve cryptosystem processors for FPGAs

In this paper we present a generator approach for the design for reuse of elliptic curve cryptosystem (ECC) processors over GF(2m), for FPGA. These accelerators are typically used in high security and high throughput environments for ensuring the security of e-commerce transactions. It is important to eliminate down-time if it is necessary to redesign an ECC accelerator to accommodate changes in speed/security requirements. Our methodology accepts a number of design parameters to specify the speed/security requirements and automatically generates a HDL description suitable for synthesis into an FPGA. We compare the real time performance of a number of ECC accelerators automatically generated using this approach.