Data bus swizzling in TSV-based three-dimensional integrated circuits

The purpose of this paper is to efficiently exploit swizzling in reducing coupling noise between the bit lines of a TSV-based data bus in three-dimensional integrated circuits. The core concept of swizzling is to distribute the noise of an aggressor to all victims, rather than concentrating on the nearest victim. Based on this principle, an optimal swizzling pattern, which achieves an equal distribution of the coupling impedance, is proposed. The efficiency of this optimal pattern is demonstrated through comparison to no swizzling and two other swizzling patterns while considering different TSV diameters, aspect ratios, pitches, and transition times of the aggressor signal. A circuit model of a TSV-based 3-D data bus is evaluated in HSPICE with each TSV modeled as an RLC impedance. A maximum reduction of 51% in peak coupling noise is achieved.

[1]  Nikil Dutt,et al.  On-Chip Communication Architectures: System on Chip Interconnect , 2008 .

[2]  John P. Fishburn,et al.  Clock Skew Optimization , 1990, IEEE Trans. Computers.

[3]  Joungho Kim,et al.  TSV modeling and noise coupling in 3D IC , 2010, 3rd Electronics System Integration Technology Conference ESTC.

[4]  Eby G. Friedman,et al.  Crosstalk modeling for coupled RLC interconnects with application to shield insertion , 2006, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[5]  S. L. Harris,et al.  Fundamentals of Digital Signal Processing Using MATLAB , 2004 .

[6]  Sujit Dey,et al.  Fault modeling and simulation for crosstalk in system-on-chip interconnects , 1999, 1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051).

[7]  Kaushik Roy,et al.  A twisted-bundle layout structure for minimizing inductive coupling noise , 2000, IEEE/ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE/ACM Digest of Technical Papers (Cat. No.00CH37140).

[8]  Javier Valls-Coquillat,et al.  Statistical power estimation for FPGAs , 2005, International Conference on Field Programmable Logic and Applications, 2005..

[9]  C.H. Chang,et al.  Yield and reliability of 3DIC technology for advanced 28nm node and beyond , 2011, 2011 Symposium on VLSI Technology - Digest of Technical Papers.

[10]  Nanju Na,et al.  A methodology for the placement and optimization of decoupling capacitors for gigahertz systems [CMOS VLSI] , 2000, VLSI Design 2000. Wireless and Digital Imaging in the Millennium. Proceedings of 13th International Conference on VLSI Design.

[11]  Lei He,et al.  Simultaneous Shield Insertion and Net Ordering for Coupled RLC Nets under Explicit Noise Constraint , 2001 .

[12]  Krishna K. Agarwal,et al.  Radio Frequency Circuit Design , 2001 .

[13]  Alberto Sangiovanni-Vincentelli,et al.  Proximity templates for modeling of skin and proximity effects on packages and high frequency interconnect , 2002, ICCAD 2002.

[14]  Robert S. Patti,et al.  Three-Dimensional Integrated Circuits and the Future of System-on-Chip Designs , 2006, Proceedings of the IEEE.

[15]  Yehea Ismail,et al.  Optimizing RLC tree delays by employing repeater insertion , 1999, Twelfth Annual IEEE International ASIC/SOC Conference (Cat. No.99TH8454).

[16]  Eby G. Friedman,et al.  Optimal clock skew scheduling tolerant to process variations , 1996, DAC '96.

[17]  J. A. Fleming,et al.  Magnets and Electric Currents, an Elementary Treatise for the Use of Electrical Artisans and Science Teachers , 2008 .

[18]  Eby G. Friedman,et al.  Interconnect-Based Design Methodologies for Three-Dimensional Integrated Circuits , 2009, Proceedings of the IEEE.

[19]  C. L. Liu,et al.  Minimum crosstalk channel routing , 1996, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[20]  Eby G. Friedman,et al.  Interconnect coupling noise in CMOS VLSI circuits , 1999, ISPD '99.

[21]  Jian Xu,et al.  Demystifying 3D ICs: the pros and cons of going vertical , 2005, IEEE Design & Test of Computers.

[22]  Yehea I. Ismail,et al.  Skewed Repeater Bus: A Low-Power Scheme for On-Chip Buses , 2008, IEEE Transactions on Circuits and Systems I: Regular Papers.

[23]  Yehea I. Ismail,et al.  Efficient model order reduction including skin effect , 2003, DAC '03.

[24]  Xiong Jie.  Realizes for Reorganizing The Fundamentals of Electric Circuits(Third Edition) , 2008 .

[25]  Renatas Jakushokas,et al.  Minimizing noise via shield and repeater insertion , 2009, 2009 IEEE International Symposium on Circuits and Systems.

[26]  A. Nahman,et al.  Wire-length distribution of three-dimensional integrated circuits , 1999, Proceedings of the IEEE 1999 International Interconnect Technology Conference (Cat. No.99EX247).

[27]  Charles K. Alexander,et al.  Fundamentals of Electric Circuits , 1999 .

[28]  Lei He,et al.  Simultaneous shield insertion and net ordering under explicit RLC noise constraint , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

[29]  Eby G. Friedman,et al.  Peak crosstalk noise estimation in CMOS VLSI circuits , 1999, ICECS'99. Proceedings of ICECS '99. 6th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.99EX357).

[30]  Yehea Ismail,et al.  Optimum repeater insertion based on a CMOS delay model for on-chip RLC interconnect , 1998, Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372).

[31]  Kaustav Banerjee,et al.  Interconnect limits on gigascale integration (GSI) in the 21st century , 2001, Proc. IEEE.

[32]  Emre Salman,et al.  Shielding Methodologies in the Presence of Power/Ground Noise , 2011, IEEE Trans. Very Large Scale Integr. Syst..

[33]  Lawrence T. Pillage,et al.  Skew And Delay Optimization For Reliable Buffered Clock Trees , 1993, Proceedings of 1993 International Conference on Computer Aided Design (ICCAD).

[34]  M. Kleiner,et al.  Interconnect capacitances, crosstalk, and signal delay in vertically integrated circuits , 1995, Proceedings of International Electron Devices Meeting.

[35]  Yehea I. Ismail,et al.  Accurate decoupling of capacitively coupled buses , 2005, 2005 IEEE International Symposium on Circuits and Systems.

[36]  Shahid Rauf,et al.  Inter-Strata Connection Characteristics and Signal Transmission in Three-Dimensional (3D) Integration Technology , 2007, 8th International Symposium on Quality Electronic Design (ISQED'07).

[37]  H. B. Dwight.  Skin Effect in Tubular and Flat Conductors , 1918, Transactions of the American Institute of Electrical Engineers.

[38]  Kunihiro Asada,et al.  An analysis on VLSI interconnection considering skin effect , 1998, Proceedings of 1998 Asia and South Pacific Design Automation Conference.

[39]  Dhanistha Panyasak,et al.  Circuits , 1995, Annals of the New York Academy of Sciences.

[40]  Malgorzata Marek-Sadowska,et al.  Crosstalk reduction for VLSI , 1997, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[41]  Eby G. Friedman.  Clock distribution networks in VLSI circuits and systems , 1995 .

[42]  Andrew B. Kahng,et al.  Interconnect optimization strategies for high-performance VLSI designs , 1999, Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013).

[43]  Eby G. Friedman,et al.  Repeater insertion in tree structured inductive interconnect , 2001 .

[44]  Andrew B. Kahng,et al.  Interconnect tuning strategies for high-performance ICs , 1998, DATE.

[45]  C.F. MURPHY,et al.  Economic analysis of test and known good die for multichip assemblies , 1994, Proceedings of 3rd International Workshop on the Economics of Design, Test and Manufacturing.

[46]  Y. Akasaka.  Three-dimensional IC trends , 1986, Proceedings of the IEEE.

[48]  John H. Lau,et al.  TSV manufacturing yield and hidden costs for 3D IC integration , 2010, 2010 Proceedings 60th Electronic Components and Technology Conference (ECTC).

[49]  E. Friedman,et al.  Closed-Form Expressions of 3-D Via Resistance, Inductance, and Capacitance , 2009, IEEE Transactions on Electron Devices.

[50]  R. Bracewell.  The Fourier Transform and Its Applications , 1966 .

[51]  John H. Lau.  The Most Cost-Effective Integrator (TSV Interposer) for 3D IC Integration System-in-Package (SiP) , 2011 .

[52]  Bassel Soudan.  Reducing mutual inductance of wide signal busses through swizzling , 2003, 10th IEEE International Conference on Electronics, Circuits and Systems, 2003. ICECS 2003. Proceedings of the 2003.

[53]  Sachin S. Sapatnekar,et al.  Timing Analysis and Optimization of Sequential Circuits , 1998 .

[54]  Dan Pitica,et al.  Statistical information of crosstalk on parallel bus , 2011, 2011 IEEE 17th International Symposium for Design and Technology in Electronic Packaging (SIITME).

[55]  T. Hughes,et al.  Signals and systems , 2006, Genome Biology.

[56]  Ron Schmitt,et al.  Electromagnetics Explained: A Handbook for Wireless/ RF, EMC, and High-Speed Electronics , 2002 .

[57]  David A. Patterson,et al.  Computer Architecture, Fifth Edition: A Quantitative Approach , 2011 .

[58]  David A. Patterson,et al.  Computer Architecture: A Quantitative Approach , 1969 .

[59]  Kartik Raol.  Interconnect and Device Scaling Trends in CMOS VLSI , 2010, 2010 International Symposium on Electronic System Design.

[60]  N. Kernevez,et al.  Challenges for 3D IC integration: bonding quality and thermal management , 2007, 2007 IEEE International Interconnect Technology Conferencee.

[61]  Roshan Weerasekera.  System Interconnection Design Trade-offs in Three-Dimensional (3-D) Integrated Circuits , 2008 .

[62]  Hannu Tenhunen,et al.  On signalling over Through-Silicon Via (TSV) interconnects in 3-D Integrated Circuits , 2010, 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010).

[63]  C. L. Liu,et al.  A postprocessing algorithm for crosstalk-driven wire perturbation , 2000, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[64]  Eby G. Friedman,et al.  Three-dimensional Integrated Circuit Design , 2008 .

[65]  R. Bracewell.  The Fourier transform. , 1989, Scientific American.

[66]  L. J. Herbst.  A critical look at interconnect scaling , 1989 .

[67]  Luca Benini,et al.  Analysis of glitch power dissipation in CMOS ICs , 1995, ISLPED '95.

[68]  Yehea I. Ismail,et al.  Repeater insertion in RLC lines for minimum propagation delay , 1999, ISCAS'99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems VLSI (Cat. No.99CH36349).

[69]  Jun Chen,et al.  A decoupling method for analysis of coupled RLC interconnects , 2002, GLSVLSI '02.

[70]  Soonhoi Ha,et al.  COP: a Crosstalk OPtimizer for gridded channel routing , 1996, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[71]  Hannu Tenhunen,et al.  Bandwidth optimization for through silicon via (TSV) bundles in 3D integrated circuits. , 2009 .

[72]  Yehea I. Ismail,et al.  Modeling skin and proximity effects with reduced realizable RL circuits , 2004, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[73]  Eby G. Friedman,et al.  Decoupling technique and crosstalk analysis for coupled RLC interconnects , 2004, 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512).

[74]  Takayasu Sakurai,et al.  Closed-form expressions for interconnection delay, coupling, and crosstalk in VLSIs , 1993 .

[75]  Anantha Chandrakasan,et al.  Three-dimensional integrated circuits: performance, design methodology, and CAD tools , 2003, IEEE Computer Society Annual Symposium on VLSI, 2003. Proceedings..

[76]  A. Farcy,et al.  TSV as an alternative to wire bonding for a wireless industrial product: another step towards 3D integration , 2010, 3rd Electronics System Integration Technology Conference ESTC.

[77]  Chenming Hu,et al.  Electromigration interconnect lifetime under AC and pulse DC stress , 1989 .

[78]  Eby G. Friedman,et al.  Delay and noise estimation of CMOS logic gates driving coupled resistive-capacitive interconnections , 2000, Integr..

[79]  Puneet Gupta,et al.  Wire swizzling to reduce delay uncertainty due to capacitive coupling , 2004, 17th International Conference on VLSI Design. Proceedings..

[80]  Bassel Soudan,et al.  Controlling Inductive Coupling in Wide Global Signal Busses Through Swizzling , 2005 .

[81]  Michael J. Brett,et al.  Three‐dimensional thermal analysis of high density triple‐level interconnection structures in very large scale integrated circuits , 1994 .

[82]  H. B. Bakoglu,et al.  Circuits, interconnections, and packaging for VLSI , 1990 .