An Experimental Power-Lines Model for Digital ASICs Based on Transmission Lines
暂无分享,去创建一个
Davide De Caro | Antonio Girardi | Roberto Izzi | Niccolò Rinaldi | M. Spirito | M. Costagliola | P. Spirito | N. Rinaldi | M. Spirito | P. Spirito | M. Costagliola | D. Caro | A. Girardi | R. Izzi
[1] Y. Yang. Design Trade-Offs for the Last Stage of Unregulated, Long-Channel CMOS Off-Chip Driver with Simultaneous Swiching Noise and Switching Time Considerations , 1996 .
[2] Falah Awwad,et al. Importance of on-chip inductance in designing RLC VLSI interconnects , 2002, The 14th International Conference on Microelectronics,.
[3] Yungseon Eo,et al. S-parameter-measurement-based high-speed signal transient characterization of VLSI interconnects on SiO/sub 2/-Si substrate , 2000 .
[4] Mark Horowitz,et al. Signal Delay in RC Tree Networks , 1983, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[5] Yan-Chyuan Shiau,et al. Generic linear RC delay modeling for digital CMOS circuits , 1990, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[6] Andrew B. Kahng,et al. An analytical delay model for RLC interconnects , 1997, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[7] A. Kabbani,et al. Estimation of ground bounce effects on CMOS circuits , 1999 .
[8] T. Sakurai,et al. Approximation of wiring delay in MOSFET LSI , 1983, IEEE Journal of Solid-State Circuits.
[9] Robert Michael Owens,et al. Modeling the effect of ground bounce on noise margin , 1994, Proceedings., International Test Conference.
[10] J. J. McKeown. Non-Linear Parameter Estimation , 1972 .
[11] Otto Richter,et al. Non-linear parameter estimation in pesticide degradation , 1992 .
[12] A. Mangan,et al. De-embedding transmission line measurements for accurate modeling of IC designs , 2006, IEEE Transactions on Electron Devices.
[13] Melvin A. Breuer,et al. Analysis of ground bounce in deep sub-micron circuits , 1997, Proceedings. 15th IEEE VLSI Test Symposium (Cat. No.97TB100125).
[14] Yehea I. Ismail,et al. Figures of merit to characterize the importance of on-chip inductance , 1998, Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175).
[15] K. Mouthaan,et al. Modelig and Simulation of Hybrid RF Circuits Using a Versatile Compact Bondwire Model , 1998, 1998 28th European Microwave Conference.
[16] Andrew B. Kahng,et al. An Analytical Delay Model for Interconnects , 1997 .