Analytic derivation of processor potential utilization in straight line, ring, square mesh, and hypercube networks

In multicomputer architectures, in which processors communicate through message-passing, the overhead encountered because of the need to relay messages can significantly affect performance. Based upon some simplifying assumptions including the rate at which a processor generates messages being proportional to its current potential utilization, processor utilizations are analytically derived in matrix form for a bidirectional straight line and square mesh. In addition, closed form derivations are provided for a unidirectional ring and an n-dimensional hypercube. Finally, the theoretical results are found to be in close agreement with discrete-event simulations of the four architectures.