Accelerated Chip-Level Thermal Analysis Using Multilayer Green's Function

Continual scaling of transistors and interconnects has exacerbated the power and thermal management problems in the design of ultralarge-scale integrated (ULSI) circuits. This paper presents an efficient thermal-analysis method of O(NlgN) complexity, where N is the number of blocks that discretize the heat-source or temperature-observation regions. The method is named LOTAGre and formulated using the Green's function for heat conduction through multiple-layer materials, which account for the structure of ULSI chips and the accompanying heat sinks and mounting accessories. In addition to analyzing the thermal effects of the distributive heat sources, LOTAGre also considers the ambient temperature effects that are generally excluded in conventional Green's function-based thermal-analysis tools in order to avoid the concomitant analytical complexity. By employing the well-known eigen-expansion technique and classical transmission-line theory, fully analytical and explicit formulas are derived in this paper for the multilayer Green's function with the inclusion of the s-domain version, the homogeneous and inhomogeneous solutions to the heat-conduction equation. Then, the discrete cosine transform and its inversion are employed to accelerate the numerical computation of the homogeneous and inhomogeneous solutions. This paper includes extensive experimental results to demonstrate that LOTAGre can be as accurate as FLUENT, a sophisticated computational fluid dynamics tool, while speeding up the simulation run time by two to three orders of magnitude in comparison to FLUENT as well as conventional Green's function-based thermal-analysis methods. This paper also discusses the limitations of using the traditional single-layer thermal model in thermal analysis for approximating a multilayer chip structure

[1]  R. W. Beatty,et al.  on Microwave Theory and Techniques , 1959 .

[2]  Sung-Mo Kang,et al.  Interconnect thermal modeling for accurate simulation of circuittiming and reliability , 2000, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[3]  Ali M. Niknejad,et al.  Numerically stable Green function for modeling and analysis of substrate coupling in integrated circuits , 1998, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[4]  G. Wachutka,et al.  Transient temperature fields with general nonlinear boundary conditions in electronic systems , 2005, IEEE Transactions on Components and Packaging Technologies.

[5]  Marta Rencz,et al.  An efficient thermal simulation tool for ICs, microsystem elements and MCMs: the μS-THERMANAL , 1998 .

[6]  Gianluca Piccinini,et al.  Clock Distribution Network Optimization under Self-Heating and Timing Constraints , 2002, PATMOS.

[7]  V. Székely,et al.  THERMODEL: a tool for compact dynamic thermal model generation , 1998 .

[8]  Paolo Maffezzoni,et al.  An Arnoldi based thermal network reduction method for electro-thermal analysis , 2003 .

[9]  A. Amerasekera,et al.  The effect of interconnect scaling and low-k dielectric on the thermal characteristics of the IC metal , 1996, International Electron Devices Meeting. Technical Digest.

[10]  Kaushik Roy,et al.  Ultra-low power DLMS adaptive filter for hearing aid applications , 2001, ISLPED '01.

[11]  Tai-Yu Chou,et al.  Capacitance calculation of IC packages using the finite element method and planes of symmetry , 1994, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[12]  Kouichi Kanda,et al.  Design impact of positive temperature dependence of drain current in sub 1 V CMOS VLSIs , 1999 .

[13]  Lawrence T. Pileggi,et al.  PRIMA: passive reduced-order interconnect macromodeling algorithm , 1997, ICCAD 1997.

[14]  P. Leturcq,et al.  Three-dimensional thermal modeling based on the two-port network theory for hybrid or monolithic integrated power circuits , 1996 .

[15]  Gianluca Piccinini,et al.  An electromigration and thermal model of power wires for a priori high-level reliability prediction , 2004, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[16]  M. Rencz,et al.  Inclusion of RC compact models of packages into board level thermal simulation tools , 2002, Eighteenth Annual IEEE Semiconductor Thermal Measurement and Management Symposium. Proceedings 2002 (Cat.No.02CH37311).

[17]  Kartikeya Mayaram,et al.  On the numerical stability of Green's function for substrate coupling in integrated circuits , 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[18]  A. Haji-sheikh,et al.  Heat Conduction Using Green's Function , 1992 .

[19]  Lawrence T. Pileggi,et al.  PRIMA: passive reduced-order interconnect macromodeling algorithm , 1998, 1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD).

[20]  Charlie Chung-Ping Chen,et al.  3-D Thermal-ADI: a linear-time chip level transient thermal simulator , 2002, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[21]  Kaustav Banerjee,et al.  3-D ICs: a novel chip design for improving deep-submicrometer interconnect performance and systems-on-chip integration , 2001, Proc. IEEE.

[22]  A. Wang,et al.  Modeling and sizing for minimum energy operation in subthreshold circuits , 2005, IEEE Journal of Solid-State Circuits.

[23]  Michael B. Steer,et al.  Electrothermal CAD of power devices and circuits with fully physical time-dependent compact thermal modeling of complex nonlinear 3-d systems , 2001 .

[24]  J. Albers,et al.  An exact recursion relation solution for the steady-state surface temperature of a general multilayer structure , 1995 .

[25]  Kouichi Kanda,et al.  Design impact of positive temperature dependence of drain current in sub 1 V CMOS VLSIs , 1999, Proceedings of the IEEE 1999 Custom Integrated Circuits Conference (Cat. No.99CH36327).

[26]  Sung-Mo Kang,et al.  ILLIADS-T: an electrothermal timing simulator for temperature-sensitive reliability diagnosis of CMOS VLSI chips , 1998, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[27]  Andras Poppe,et al.  THERMAN: a thermal simulation tool for IC chips, microstructures and PW boards , 2000 .

[28]  Jacob K. White,et al.  FastCap: a multipole accelerated 3-D capacitance extraction program , 1991, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[29]  Ruel V Churchill Prof Fourier Series and Boundary Value Problems , 1942, Nature.

[30]  N. Ahmed,et al.  Discrete Cosine Transform , 1996 .

[31]  Kevin Skadron,et al.  Compact thermal modeling for temperature-aware design , 2004, Proceedings. 41st Design Automation Conference, 2004..

[32]  G. B. Kromann,et al.  The development of component-level thermal compact models of a C4/CBGA interconnect technology: the Motorola PowerPC 603/sup TM/ and PowerPC 604/sup TM/ RISC microprocessors , 1996, 1996 Proceedings 46th Electronic Components and Technology Conference.

[33]  Alberto L. Sangiovanni-Vincentelli,et al.  On thermal effects in deep sub-micron VLSI interconnects , 1999, DAC '99.

[34]  Raymond Crampagne,et al.  A Simple Method for Determining the Green's Function for a Large Class of MIC Lines Having Multilayered Dielectric Structures , 1978 .

[35]  Pinaki Mazumder,et al.  Fast thermal analysis for VLSI circuits via semi-analytical Green's function in multi-layer materials , 2004, 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512).

[36]  D. Maillet,et al.  Thermal Quadrupoles: Solving the Heat Equation through Integral Transforms , 2000 .

[37]  Jacob K. White,et al.  A precorrected-FFT method for electrostatic analysis of complicated 3-D structures , 1997, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[38]  Ishiuchi,et al.  Alpha-Power Law MOSFET Model and its Applications to CMOS Inverter Delay and Other Formulas , 2004 .

[39]  Yong Zhan,et al.  Fast computation of the temperature distribution in VLSI chips using the discrete cosine transform and table look-up , 2005, Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005..

[40]  Gerhard Wachutka,et al.  Time dependent temperature fields calculated using eigenfunctions and eigenvalues of the heat conduction equation , 2001 .

[41]  Sung-Mo Kang,et al.  A temperature-aware simulation environment for reliable ULSI chipdesign , 2000, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[42]  A. G. Kokkas Thermal analysis of multiple-layer structures , 1974 .

[43]  D. Pozar Microwave Engineering , 1990 .

[44]  G. Hill,et al.  Flip-chip encapsulation on ceramic substrates , 1993, Proceedings of IEEE 43rd Electronic Components and Technology Conference (ECTC '93).

[45]  Mark A. Clements,et al.  Digital Signal Processing and Statistical Classification , 2002 .

[46]  V. Szekely,et al.  Identification of RC networks by deconvolution: chances and limits , 1998 .