Modeling and Analysis of Through-Silicon Via (TSV) Noise Coupling and Suppression Using a Guard Ring
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Junho Lee | Joungho Kim | Jun So Pak | Taigon Song | Woojin Lee | Eakhwan Song | Jonghyun Cho | Joohee Kim | Kiyeong Kim | Hyungdong Lee | Kunwoo Park | Kihyun Yoon | Seungtaek Yang | Minsuk Suh | Kwangyoo Byun | Taigon Song | Joungho Kim | Jonghyun Cho | Kiyeong Kim | Woojin Lee | Joohee Kim | J. Pak | Hyungdong Lee | Kunwoo Park | Junho Lee | Eakhwan Song | Kwang-yoo Byun | M. Suh | Kihyun Yoon | Seungtaek Yang | Kiyeong Kim
[1] Jaemin Kim,et al. Modeling and Analysis of Power Supply Noise Imbalance on Ultra High Frequency Differential Low Noise Amplifiers in a System-in-Package , 2010, IEEE Transactions on Advanced Packaging.
[2] Lijun Jiang,et al. Electrical-thermal co-analysis for power delivery networks in 3D system integration , 2009, 2009 IEEE International Conference on 3D System Integration.
[3] C. Christopoulos,et al. The Transmission-line Modeling Method: TLM , 1995, IEEE Antennas and Propagation Magazine.
[4] H. Reichl,et al. Managing Losses in Through Silicon Vias with Different Return Current Path Configurations , 2008, 2008 10th Electronics Packaging Technology Conference.
[5] Sung Kyu Lim,et al. Co-design of signal, power, and thermal distribution networks for 3D ICs , 2009, 2009 Design, Automation & Test in Europe Conference & Exhibition.
[6] Kinam Kim,et al. Three Dimensionally Stacked NAND Flash Memory Technology Using Stacking Single Crystal Si Layers on ILD and TANOS Structure for Beyond 30nm Node , 2006, 2006 International Electron Devices Meeting.
[7] Joungho Kim,et al. High Frequency Electrical Model of Through Wafer Via for 3-D Stacked Chip Packaging , 2006, 2006 1st Electronic Systemintegration Technology Conference.
[8] J. Meindl,et al. Limits on silicon nanoelectronics for terascale integration. , 2001, Science.
[9] S. Wong,et al. Physical modeling of spiral inductors on silicon , 2000 .
[10] Howard Falk,et al. Prolog to Substrate Noise Coupling in SoC Design: Modeling, Avoidance, and Validation , 2006, Proc. IEEE.
[11] Frank Leferink,et al. Inductance calculations; methods and equations , 1995, Proceedings of International Symposium on Electromagnetic Compatibility.
[12] B. Razavi. Monolithic phase-locked loops and clock recovery circuits : theory and design , 1996 .
[13] G. Cibrario,et al. Through-silicon via based 3D IC technology: Electrostatic simulations for design methodology , 2008 .
[14] Yang Liu,et al. Reliability study of through-silicon via (TSV) copper filled interconnects , 2009 .
[15] Ali Afzali-Kusha,et al. Substrate Noise Coupling in SoC Design: Modeling, Avoidance, and Validation , 2006, Proceedings of the IEEE.
[16] Katsuyuki Sakuma,et al. Three-dimensional silicon integration , 2008, IBM J. Res. Dev..
[17] Jaemin Kim,et al. Modeling and Analysis of Simultaneous Switching Noise Coupling for a CMOS Negative-Feedback Operational Amplifier in System-in-Package , 2009, IEEE Transactions on Electromagnetic Compatibility.
[18] Taigon Song,et al. Modeling and analysis of coupling between TSVs, metal, and RDL interconnects in TSV-based 3D IC with silicon interposer , 2009, 2009 11th Electronics Packaging Technology Conference.
[19] Soha Hassoun,et al. Through-Silicon Via (TSV)-induced noise characterization and noise mitigation using coaxial TSVs , 2009, 2009 IEEE International Conference on 3D System Integration.
[20] Mohammed Ismail,et al. The CHIP - A Design Guide for Reducing Substrate Noise Coupling in RF Applications , 2006 .
[21] Franco Stellari,et al. New formulas of interconnect capacitances based on results of conformal mapping method , 2000 .
[22] Joungho Kim,et al. Electrical characterization of trough silicon via (TSV) depending on structural and material parameters based on 3D full wave simulation , 2007, 2007 International Conference on Electronic Materials and Packaging.