SEMICONDUCTOR INTEGRATED CIRCUITS: Testing content addressable memories with physical fault models

Content addressable memory (CAM) is widely used and its tests mostly use functional fault models. However, functional fault models cannot describe some physical faults exactly. This paper introduces physical fault models for write-only CAM. Two test algorithms which can cover 100% targeted physical faults are also proposed. The algorithm for a CAM module with N-bit match output signal needs only 2N+2L+4 comparison operations and 5N writing operations, where N is the number of words and L is the word length. The algorithm for a HIT-signal-only CAM module uses 2N+2L+5 comparison operations and 8N writing operations. Compared to previous work, the proposed algorithms can test more physical faults with a few more operations. An experiment on a test chip shows the effectiveness and efficiency of the proposed physical fault models and algorithms.