Thermal-Aware Non-slicing VLSI Floorplanning Using a Smart Decision-Making PSO-GA Based Hybrid Algorithm

Floorplanning is an important physical design step in the ASIC design flow. It is the process of estimating the area to be occupied by various blocks in a layout together with a precise interconnection pattern. In this work, a smart decision-making hybrid particle swarm optimization-genetic algorithm that aims at reducing the area, wirelength, and hotspot by distributing the temperature evenly across the chip is presented. B*-tree is used to generate the initial floorplan and later a PSO-GA based hybrid algorithm is used to obtain an optimal placement solution. Temperature-driven floorplanning is considered at the perturbation stage to separate the hotspots, thereby reducing the average and maximum temperature. The experimental results of the proposed algorithm are compared with other stochastic algorithms using MCNC and Alpha processor floorplan benchmark circuits. The result shows that the proposed algorithm performs efficient floorplanning, with reduced average and peak temperature.

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