Evaluation of line-edge roughness in Cu/low-k interconnect patterns with CD-SEM
暂无分享,去创建一个
[1] C.H. Diaz,et al. An experimentally validated analytical model for gate line-edge roughness (LER) effects on technology scaling , 2001, IEEE Electron Device Letters.
[2] T. Takeuchi,et al. Robust porous SiOCH/Cu interconnects with ultrathin sidewall protection liners , 2006, IEEE Transactions on Electron Devices.
[3] W. Zhang,et al. Impact of line edge roughness on copper interconnects , 2006 .
[4] Atsuko Yamaguchi,et al. Spectral analysis of line-edge roughness in polyphenol EB-resists and its impact on transistor performance , 2005 .
[5] John L. Sturtevant,et al. Experimental determination of the impact of polysilicon LER on sub-100-nm transistor performance , 2001, SPIE Advanced Lithography.
[6] Shiying Xiong,et al. Gate line-edge roughness effects in 50-nm bulk MOSFET devices , 2002, SPIE Advanced Lithography.
[7] Manfred Engelhardt,et al. Impact of line edge roughness on the resistivity of nanometer-scale interconnects , 2004 .