MPSoCBench: A benchmark for high-level evaluation of multiprocessor system-on-chip tools and methodologies

Abstract Recent design methodologies and tools aim at enhancing the design productivity by providing a software development platform before defining the final MPSoC architecture details. Motivated by the lack of MPSoC virtual platforms prototyping integrating both scalable hardware and software in order to create and evaluate new methodologies and tools, we present the MPSoCBench, a scalable set of MPSoCs including four different ISAs (PowerPC, MIPS, SPARC, and ARM) organized in platforms with up to 64 cores, cross-compilers, IPs, interconnections, 17 parallel versions of software from well-known benchmarks, and power consumption estimation for main components (processors, routers, memory, and caches), including DVFS support.

[1]  Somayeh Sardashti,et al.  The gem5 simulator , 2011, CARN.

[2]  Rodolfo Azevedo,et al.  An automatic energy consumption characterization of processors using ArchC , 2013, J. Syst. Archit..

[3]  Fernando Gehm Moraes,et al.  HERMES: an infrastructure for low area overhead packet-switching networks on chip , 2004, Integr..

[4]  Rodolfo Azevedo,et al.  MultiExplorer: A tool set for multicore system-on-chip design exploration , 2015, 2015 IEEE 26th International Conference on Application-specific Systems, Architectures and Processors (ASAP).

[5]  R. Azevedo,et al.  An efficient framework for high-level power exploration , 2007, 2007 50th Midwest Symposium on Circuits and Systems.

[6]  David C. Snowdon,et al.  Power Management and Dynamic Voltage Scaling: Myths and Facts , 2005 .

[7]  Courtenay T. Vaughan,et al.  Energy-Efficient High Performance Computing: Measurement and Tuning , 2012, HiPC 2012.

[8]  Cécile Belleudy,et al.  Power Consumption Modeling for DVFS Exploitation , 2010, 2010 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools.

[9]  Rodolfo Azevedo,et al.  MPSoCBench: A toolset for MPSoC system level evaluation , 2014, 2014 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XIV).

[10]  Margaret Martonosi,et al.  Wattch: a framework for architectural-level power analysis and optimizations , 2000, Proceedings of 27th International Symposium on Computer Architecture (IEEE Cat. No.RS00201).

[11]  Ronald G. Dreslinski,et al.  The M5 Simulator: Modeling Networked Systems , 2006, IEEE Micro.

[12]  Alain Greiner,et al.  Parallel simulation of systemC TLM 2.0 compliant MPSoC on SMP workstations , 2010, 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010).

[13]  Luca Benini,et al.  MPARM: Exploring the Multi-Processor SoC Design Space with SystemC , 2005, J. VLSI Signal Process..

[14]  Trevor Mudge,et al.  MiBench: A free, commercially representative embedded benchmark suite , 2001 .

[15]  Håkan Grahn,et al.  ParMiBench - An Open-Source Benchmark for Embedded Multiprocessor Systems , 2010, IEEE Computer Architecture Letters.

[16]  Fernando Gehm Moraes,et al.  A method for NoC-based MPSoC energy consumption estimation , 2014, 2014 21st IEEE International Conference on Electronics, Circuits and Systems (ICECS).

[17]  Kevin P. Lawton.  Bochs: A Portable PC Emulator for Unix/X , 1996 .

[18]  Sharad Malik,et al.  Power analysis of embedded software: a first step towards software power minimization , 1994, IEEE Trans. Very Large Scale Integr. Syst..

[19]  Jung Ho Ahn,et al.  McPAT: An integrated power, area, and timing modeling framework for multicore and manycore architectures , 2009, 2009 42nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).

[20]  Fredrik Larsson,et al.  Simics: A Full System Simulation Platform , 2002, Computer.

[21]  Anoop Gupta,et al.  The SPLASH-2 programs: characterization and methodological considerations , 1995, ISCA.

[22]  Jose Renau,et al.  ESESC: A fast multicore simulator using Time-Based Sampling , 2013, 2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA).

[23]  Milo M. K. Martin,et al.  Multifacet's general execution-driven multiprocessor simulator (GEMS) toolset , 2005, CARN.

[24]  Gilles Sassatelli,et al.  Accuracy evaluation of GEM5 simulator system , 2012, 7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC).

[25]  Rodolfo Azevedo,et al.  The ArchC Architecture Description Language and Tools , 2005, International Journal of Parallel Programming.

[26]  Liana Dessandre Duenha Garanhani.  MPSoCBench: um framework para avaliação de ferramentas e metodologias para sistemas multiprocessados em chip , 2015 .

[27]  Julio Sahuquillo,et al.  Multi2Sim: A Simulation Framework to Evaluate Multicore-Multithreaded Processors , 2007 .

[28]  Bruce Jacob,et al.  DRAMSim2: A Cycle Accurate Memory System Simulator , 2011, IEEE Computer Architecture Letters.

[29]  Stefanos Kaxiras,et al.  Introducing DVFS-Management in a Full-System Simulator , 2013, 2013 IEEE 21st International Symposium on Modelling, Analysis and Simulation of Computer and Telecommunication Systems.

[30]  Luca Benini,et al.  Cycle-accurate power analysis for multiprocessor systems-on-a-chip , 2004, GLSVLSI '04.