Compact modeling of a flash memory cell including substrate-bias-dependent hot-electron gate current

We propose a compact model for a Flash memory cell that is suitable for circuit simulation. The model includes a hot-electron gate current model that considers not only channel hot electron injection but also channel initiated secondary electron injection to express properly substrate bias dependence of gate current. Tunneling gate current for erasing is expressed by the BSIM4 tunneling gate current model. Good agreement between measured and simulated results of both programming and erasing characteristics for 130-nm technology Flash memory cells indicates that our model is useful in designing and optimizing circuit for Flash memories.

[1]  B. Eitan,et al.  Hot-electron injection into the oxide in n-channel MOS devices , 1981, IEEE Transactions on Electron Devices.

[2]  C. Hu,et al.  Lucky-electron model of channel hot-electron injection in MOSFET'S , 1984 .

[3]  Ping K. Ko,et al.  Chapter 1 - Approaches to Scaling , 1989 .

[4]  S. Mahapatra,et al.  Drain disturb during CHISEL programming of NOR flash EEPROMs-physical mechanisms and impact of technological parameters , 2004, IEEE Transactions on Electron Devices.

[5]  Luca Selmi,et al.  A better understanding of substrate enhanced gate current in VLSI MOSFETs and flash cells. II. Physical analysis , 1999 .

[6]  F. Gigon.  Modeling and simulation of the 16 megabit EPROM cell for write/read operation with a compact SPICE model , 1990, International Technical Digest on Electron Devices.

[7]  Piero Olivo,et al.  Flash memory cells-an overview , 1997, Proc. IEEE.

[8]  Chenming Hu,et al.  Hot-electron-induced photon and photocarrier generation in Silicon MOSFET's , 1984, IEEE Transactions on Electron Devices.

[9]  C. Hu.  Lucky-electron model of channel hot electron emission , 1979, 1979 International Electron Devices Meeting.

[10]  Chenming Hu,et al.  Ultra-thin silicon dioxide leakage current and scaling limit , 1992, 1992 Symposium on VLSI Technology Digest of Technical Papers.

[11]  Souvik Mahapatra,et al.  CHISEL flash EEPROM. II. Reliability , 2002 .

[12]  R. V. Overstraeten,et al.  Measurement of the ionization rates in diffused silicon p-n junctions , 1970 .

[13]  David Esseni,et al.  A better understanding of substrate enhanced gate current in VLSI MOSFET's and flash cells. I. Phenomenological aspects , 1999 .

[14]  S.S. Chung,et al.  A Spice-compatible flash EEPROM model feasible for transient and program/erase cycling endurance simulation , 1999, International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318).

[15]  J. Bude.  Gate current by impact ionization feedback in sub-micron MOSFET technologies , 1995, 1995 Symposium on VLSI Technology. Digest of Technical Papers.

[16]  R. K. Smith,et al.  Monte Carlo simulation of the CHISEL flash memory cell , 2000 .

[17]  M.R. Pinto,et al.  Secondary Electron flash-a high performance, low power flash technology for 0.35 /spl mu/m and below , 1997, International Electron Devices Meeting. IEDM Technical Digest.

[18]  J. Higman,et al.  Nonlocality of the electron ionization coefficient in n-MOSFETs: an analytic approach , 1988, IEEE Electron Device Letters.

[19]  Souvik Mahapatra,et al.  CHISEL flash EEPROM. I. Performance and scaling , 2002 .

[20]  A. Frommer,et al.  EEPROM/flash sub 3.0 V drain-source bias hot carrier writing , 1995, Proceedings of International Electron Devices Meeting.

[21]  J. Bude.  Secondary electron flash-A high performance, low power flash technology for 0.35μm and below , 1997 .

[22]  Luca Larcher,et al.  A New Analytical Model of Channel Hot Electron (CHE) and CHannel Initiated Secondary ELectron (CHISEL) Current Suitable for Compact Modeling , 2002 .

[23]  D. Esseni,et al.  Experimental signature and physical mechanisms of substrate enhanced gate current in MOS devices , 1998, International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217).

[24]  Kenji Taniguchi,et al.  Nonlocal Impact Ionization Model and Its Application to Substrate Current Simulation of n-MOSFET's , 1995 .

[25]  G. Baccarani,et al.  An investigation of steady-state velocity overshoot in silicon , 1985 .