MD-SCAN method for low power scan testing

As semiconductor manufacturing technology advances, power dissipation and noise in scan testing have become critical problems. Our studies on practical LSI manufacturing show that power supply voltage drop causes testing problems during shift operations in scan testing. In this paper, we present a new testing method named MD-SCAN (multi duty-scan) which solves power supply voltage drop problems, as well as its experimental results applied to practical LSI chips.

[1]  Nur A. Touba,et al.  Reducing power dissipation during test using scan chain disable , 2001, Proceedings 19th IEEE VLSI Test Symposium. VTS 2001.

[2]  Lee Whetsel,et al.  Adapting scan architectures for low power operation , 2000, Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159).

[3]  Bashir M. Al-Hashimi,et al.  Scan latch partitioning into multiple scan chains for power minimization in full scan sequential circuits , 2000, DATE '00.

[4]  Zebo Peng,et al.  Test scheduling and scan-chain division under power constraint , 2001, Proceedings 10th Asian Test Symposium.

[5]  S. Pravossoudovitch,et al.  A gated clock scheme for low power scan testing of logic ICs or embedded cores , 2001, Proceedings 10th Asian Test Symposium.

[6]  Kuen-Jong Lee,et al.  A token scan architecture for low power testing , 2001, Proceedings International Test Conference 2001 (Cat. No.01CH37260).

[7]  Vishwani D. Agrawal,et al.  Scheduling tests for VLSI systems under power constraints , 1997, IEEE Trans. Very Large Scale Integr. Syst..

[8]  L. Whetsel,et al.  An analysis of power reduction techniques in scan testing , 2001, Proceedings International Test Conference 2001 (Cat. No.01CH37260).