论文信息 - Current-mode CMOS multiplier/divider circuit operating in linear/saturation regions

Current-mode CMOS multiplier/divider circuit operating in linear/saturation regions

A CMOS current-mode analog multiplier/divider circuit is presented. It is suited to standard CMOS fabrication and can be successfully employed in a wide range of analog signal processing applications. Measurement results for a 0.5 μm CMOS test chip prototype verify the approach employed. The circuit consumes 120 μW using a single supply voltage of 1.5 V and requires a silicon area of 150 × 140 μm.

Jaime Ramirez-Angulo | Ramon G. Carvajal | Antonio J. Lopez-Martin | Carlos A. La Cruz Blas

[1] James J. Clark,et al. A four-quadrant CMOS analog multiplier for analog neural networks , 1994, IEEE J. Solid State Circuits.

[2] Antonio J. López-Martín,et al. Current-Mode Multiplier/Divider Circuits Based on the MOS Translinear Principle , 2001 .

[3] Jaime Ramírez-Angulo. Highly Linear Four Quadrant Analog BiCMOS Multiplier for ± 1.5 V Supply Operation , 1993, ISCAS.