Testing layered interconnection networks

This paper presents an approach for fault detection in layered interconnection networks (LINs). A LIN is a generalized multistage interconnection network commonly used in reconfigurable systems; the nets (links) are arranged in sets (referred to as layers) of different size. A comprehensive fault model for the nets and switches is assumed at physical and behavioral levels. Testing requires to configure the LIN multiple times. Using a graph approach, it is proved that the minimal set of configurations corresponds to the node disjoint path sets. The proposed approach is based on two novel results inn the execution of the network flow algorithm to find node disjoint path sets, while retaining optimality in the number of configurations. These objectives are accomplished by finding a feasible flow, such that the maximal degree can be iteratively decreased, while guaranteeing the existence of art appropriate circulation. Net adjacencies are also tested for possible bridge faults (shorts). To account for 100 % fault coverage of bridge faults a post-processing algorithm may be required; bounds on its complexity are provided. The execution complexity of the proposed approach (inclusive of test vector generation and post-processing) is O(N/sup 4/W L), where N is the total number of nets, W is the number of switches per switching element and L is the number of layers. Extensive simulation results are provided.

[1]  Fabrizio Lombardi,et al.  On the Constant Diagnosability of Baseline Interconnection Networks , 1990, IEEE Trans. Computers.

[2]  Jeffrey D Ullma Computational Aspects of VLSI , 1984 .

[3]  David A. Padua,et al.  Interconnection Networks Using Shuffles , 1981, Computer.

[4]  Tse-Yun Feng,et al.  On a Class of Multistage Interconnection Networks , 1980, IEEE Transactions on Computers.

[5]  Tse-Yun Feng,et al.  Fault-Diagnosis for a Class of Multistage Interconnection Networks , 1981, IEEE Trans. Computers.

[6]  Fabrizio Lombardi,et al.  A coloring approach to the structural diagnosis of interconnects , 1996, ICCAD 1996.

[7]  Fabrizio Lombardi,et al.  On the diagnosis of programmable interconnect systems: Theory and application , 1996, Proceedings of 14th VLSI Test Symposium.

[8]  Stephen D. Brown,et al.  Flexibility of interconnection structures for field-programmable gate arrays , 1991 .

[9]  Wojciech Maly,et al.  Circuit design for a large area high-performance crossbar switch , 1991, [Proceedings] 1991 International Workshop on Defect and Fault Tolerance on VLSI Systems.

[10]  Alan J. Hoffman,et al.  SOME RECENT APPLICATIONS OF THE THEORY OF LINEAR INEQUALITIES TO EXTREMAL COMBINATORIAL ANALYSIS , 2003 .

[11]  Vaughn Betz,et al.  Automatic generation of FPGA routing architectures from high-level descriptions , 2000, FPGA '00.

[12]  Najmi T. Jarwala,et al.  A unified theory for designing optimal test generation and diagnosis algorithms for board interconnects , 1989, Proceedings. 'Meeting the Tests of Time'., International Test Conference.

[13]  Miroslaw Malek,et al.  Comprehensive Testing of Multistage Interconnection Networks , 1991, IEEE Trans. Computers.

[14]  Vinod K. Agarwal,et al.  Testing and diagnosis of interconnects using boundary scan architecture , 1988, International Test Conference 1988 Proceeding@m_New Frontiers in Testing.

[15]  Derek F. Wong,et al.  Universal Switch-Module Design for Symmetric-Array-Based FPGAs , 1996, Fourth International ACM Symposium on Field-Programmable Gate Arrays.

[16]  Mark A. Franklin,et al.  VLSI Performance Comparison of Banyan and Crossbar Communications Networks , 1981, IEEE Transactions on Computers.

[17]  Jonathan Rose,et al.  A hybrid complete-graph partial-crossbar routing architecture for multi-FPGA systems , 1998, FPGA '98.

[18]  Guy Lemieux,et al.  Generating highly-routable sparse crossbars for PLDs , 2000, FPGA '00.

[19]  Wu-Tung Cheng,et al.  Diagnosis for wiring interconnects , 1990, Proceedings. International Test Conference 1990.

[20]  J. Van Leeuwen,et al.  Handbook of theoretical computer science - Part A: Algorithms and complexity; Part B: Formal models and semantics , 1990 .

[21]  William H. Kautz,et al.  Testing for Faults in Wiring Networks , 1974, IEEE Transactions on Computers.

[22]  Fabrizio Lombardi,et al.  Detection and Location of Multiple Faults in Baseline Interconnection Networks , 1992, IEEE Trans. Computers.