Optimizing Static Power Dissipation by Functional Units in Superscalar Processors
暂无分享,去创建一个
[1] Santa Barbara,et al. of Arizona Tucson, Arizona 85721 , 1989 .
[2] Christopher W. Fraser,et al. A Retargetable C Compiler: Design and Implementation , 1995 .
[3] Kaushik Roy,et al. Gated-Vdd: a circuit technique to reduce leakage in deep-submicron cache memories , 2000, ISLPED '00.
[4] Qi Wang,et al. Static power optimization of deep submicron CMOS circuits for dual V/sub T/ technology , 1998, 1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287).
[5] M. Horowitz,et al. Low-power digital design , 1994, Proceedings of 1994 IEEE Symposium on Low Power Electronics.
[6] Sharad Malik,et al. Dynamic power management for microprocessors: a case study , 1997, Proceedings Tenth International Conference on VLSI Design.
[7] Vivek Tiwari,et al. Reducing power in high-performance microprocessors , 1998, Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175).
[8] Gurindar S. Sohi,et al. A static power model for architects , 2000, MICRO 33.
[9] Rajiv Gupta,et al. Automatic generation of microarchitecture simulators , 1998, Proceedings of the 1998 International Conference on Computer Languages (Cat. No.98CB36225).
[10] Kaushik Roy. Leakage power reduction in low-voltage CMOS designs , 1998, 1998 IEEE International Conference on Electronics, Circuits and Systems. Surfing the Waves of Science and Technology (Cat. No.98EX196).
[11] Miodrag Potkonjak,et al. MediaBench: a tool for evaluating and synthesizing multimedia and communications systems , 1997, Proceedings of 30th Annual International Symposium on Microarchitecture.
[12] Margaret Martonosi,et al. Wattch: a framework for architectural-level power analysis and optimizations , 2000, Proceedings of 27th International Symposium on Computer Architecture (IEEE Cat. No.RS00201).