An FPGA-based Face Recognition Using Combined 5/3 DWT with PCA Methods

This paper describes a new scheme for feature extraction from facial images on FPGA, The proposed method is comprised of two stages. The first stage uses the 5/3 DWT to decompose the original face image into LL, LH, HL, and HH wavelet coefficient to reduce the size of the image. In the second stage, PCA is employed to extract the face features from the wavelet coefficients. Here we use the power iteration algorithm to find the eigenvector of the covariance matrix. We present an efficient hardware architecture using combination of parallel processing module and serial processing module. This method can take the benefits of parallel usage advantage of FPGAs and can save hardware resources. Complete hardware implemented on a Stratix Ⅱ FPGA. The experimental results show that the system works with high processing rate and only 21 % of the logic resources an FPGA are consumed by face recognition logic. Thus it is very suitable for the low cost implementation of the face recognition system.