A 90 nm CMOS 15/60 GHz frequency quadrupler

The design and characterisation of a 60 GHz frequency quadrupler implemented in a conventional 90 nm CMOS technology is presented. The proposed fully differential frequency quadrupler is formed by properly combining a 15 GHz to 30 GHz doubler, two 30 GHz amplifiers, a polyphase filter, a 30 to 60 GHz doubler and two 60 GHz amplifiers. The proposed design is based on a differential architecture and achieves enhanced characteristics in terms of harmonics rejection, bandwidth, power consumption and die area. Conversion loss of 9.3 dBm at 60 GHz with 1.1 dBm input power is achieved. The 3 dB bandwidth lies between 51.5 GHz and 61 GHz, while the total current consumption is 100 mA from a 1.2 V supply voltage for the fully balanced implementation.

[1]  Asad A. Abidi,et al.  CMOS mixers and polyphase filters for large image rejection , 2001, IEEE J. Solid State Circuits.

[2]  K. Komoni,et al.  Fundamental performance limits and scaling of a CMOS passive double-balanced mixer , 2008, 2008 Joint 6th International IEEE Northeast Workshop on Circuits and Systems and TAISA Conference.

[3]  Herbert Zirath,et al.  High-purity 60-GHz-band single-chip x 8 multipliers in pHEMT and mHEMT technology , 2006 .

[4]  Christian Fager,et al.  60 GHz Single-Chip Front-End MMICs and Systems for Multi-Gb/s Wireless Communication , 2007, IEEE Journal of Solid-State Circuits.

[5]  John R. Long,et al.  A 56-to-65GHz Injection-Locked Frequency Tripler with Quadrature Outputs in 90nm CMOS , 2008, 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

[6]  Gang Liu,et al.  60–80 GHz frequency doubler operating close to fmax , 2010, 2010 Asia-Pacific Microwave Conference.

[7]  C. Karnfelt,et al.  High-purity 60-GHz-band single-chip /spl times/8 multipliers in pHEMT and mHEMT technology , 2006, IEEE Transactions on Microwave Theory and Techniques.

[8]  T. Morimoto,et al.  Highly Integrated 60 GHz-band x12 Multiplier MMIC , 2006, 2006 IEEE MTT-S International Microwave Symposium Digest.

[9]  J.R. Long,et al.  A 56–65 GHz Injection-Locked Frequency Tripler With Quadrature Outputs in 90-nm CMOS , 2008, IEEE Journal of Solid-State Circuits.

[10]  K. Okada,et al.  60 GHz injection locked frequency quadrupler with quadrature outputs in 65 nm CMOS process , 2009, Asia-Pacific Microwave Conference.

[11]  M. Schefer.  Integrated quadrupler circuit in coplanar technology for 60 GHz wireless applications , 2002, 2002 IEEE MTT-S International Microwave Symposium Digest (Cat. No.02CH37278).

[12]  H. Zirath,et al.  40 and 60 GHz frequency doublers in 90-nm CMOS , 2004, 2004 IEEE MTT-S International Microwave Symposium Digest (IEEE Cat. No.04CH37535).

[13]  Kwang-Seok Seo,et al.  60 GHz flip-chip mounted frequency doubler/PA chain MMIC with low input power and high output power , 2008, 2008 IEEE Radio and Wireless Symposium.

[14]  M. Kantanen,et al.  60 GHz Frequency Conversion 90 nm CMOS Circuits , 2008, 2008 European Microwave Integrated Circuit Conference.

[15]  H. Sjoland,et al.  A polyphase filter based on CMOS inverters , 2005, 2005 NORCHIP.

[16]  H. Zirath,et al.  Development of 60-GHz front-end circuits for a high-data-rate communication system , 2004, IEEE Journal of Solid-State Circuits.