Variations-Aware Low-Power Design and Block Clustering With Voltage Scaling

We present a new methodology which takes into consideration the effect of within-die (WID) process variations on a low-voltage parallel system. We show that in the presence of process variations one should use a higher supply voltage than would otherwise be predicted to minimize the power consumption of a parallel systems. Previous analyses, which ignored WID process variations, provide a lower nonoptimal supply voltage which can underestimate the energy/operation by 8.2. We also present a novel technique to limit the effect of temperature variations in a parallel system. As temperatures increases, the scheme reduces the power increase by 43% allowing the system to remain at it's optimal supply voltage across different temperatures. To further limit the effect of variations, and allow for a reduced power consumption, we analyzed the effects of clustering. It was shown that providing different voltages to each cluster can provide a further 10% reduction in energy/operation to a low-voltage parallel system, and that the savings by clustering increase as technology scales.

[1]  Sani R. Nassif,et al.  Models of process variations in device and interconnect , 2000 .

[2]  Stefan Kubicek,et al.  Analysis of leakage currents and impact on off-state power consumption for CMOS technology in the 100-nm regime , 2000 .

[3]  Benton H. Calhoun,et al.  Device sizing for minimum energy operation in subthreshold circuits , 2004 .

[4]  Qing Su,et al.  An IC manufacturing yield model considering intra-die variations , 2006, 2006 43rd ACM/IEEE Design Automation Conference.

[5]  Doris Schmitt-Landsiedel,et al.  The impact of intra-die device parameter variations on path delays and on the design for yield of low voltage digital circuits , 1996, ISLPED '96.

[6]  C. Lichtenau,et al.  A 64B CPU Pair: Dual- and Single-Processor Chips , 2006, 2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers.

[7]  C. Webb,et al.  A scalable X86 CPU design for 90 nm process , 2004, 2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519).

[8]  Chandu Visweswariah,et al.  Death, taxes and failing chips , 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).

[9]  Christer Svensson,et al.  Trading speed for low power by choice of supply and threshold voltages , 1993 .

[10]  Anantha Chandrakasan,et al.  Models of Process Variations in Device and Interconnect , 2001 .

[11]  Shin'ichiro Mutoh,et al.  1-V power supply high-speed digital circuit technology with multithreshold-voltage CMOS , 1995, IEEE J. Solid State Circuits.

[12]  Kaushik Roy,et al.  Ultra-low power DLMS adaptive filter for hearing aid applications , 2001, ISLPED '01.

[13]  S. Nassif,et al.  Delay variability: sources, impacts and trends , 2000, 2000 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.00CH37056).

[14]  David Blaauw,et al.  Analysis and mitigation of variability in subthreshold design , 2005, ISLPED '05. Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005..

[15]  David Blaauw,et al.  Simultaneous subthreshold and gate-oxide tunneling leakage current analysis in nanometer CMOS design , 2003, Fourth International Symposium on Quality Electronic Design, 2003. Proceedings..

[16]  Vivek De,et al.  Variations-aware low-power design with voltage scaling , 2005, Proceedings. 42nd Design Automation Conference, 2005..

[17]  M. Golden,et al.  A 2.6GHz Dual-Core 64bx86 Microprocessor with DDR2 Memory Support , 2006, 2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers.

[18]  Anantha P. Chandrakasan,et al.  Low Power Digital CMOS Design , 1995 .

[19]  Yuan Taur,et al.  Device scaling limits of Si MOSFETs and their application dependencies , 2001, Proc. IEEE.

[20]  E. Alon,et al.  The implementation of a 2-core, multi-threaded itanium family processor , 2006, IEEE Journal of Solid-State Circuits.

[21]  James Tschanz,et al.  Parameter variations and impact on circuits and microarchitecture , 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).