STATE ASSIGNMENT FOR INITIALIZABLE SYNTHESIS

Previous work on automatic state assignment for finite state machines is primarily aimed at reducing the amount of logic in the final Implementation. It is shown that a machine, whose state encoding is obtained by these methods, may not be ini- tializable by a logic simulator or a test generator even when the design is functionally initializable (i.e., has synchronizing sequences). A fault simulator or a sequential circuit test generator, that assumes all memory elements initially to be in the unknown state, will be totally Ineffective for such a design. Proper con- sideration for initiaiizability during state assignment can guarantee the SLICC~SS for gate level analysis tools. In this paper, the neces- sary and sufficient conditions for initializability are derived. Our new state assignment algorithm uses additional constraints for ini- tialization by a preselected input sequence. Experimental results show that, in most cases, this method does not require more hardware than the other methods that may produce an uninitializ- able design. A partial reset technique is suggested for machines without a synchronizing sequence.