Hardware accelerated SAT solvers - A survey

Abstract Boolean Satisfiability (SAT) is a problem that holds great importance both theoretically and in practical applications. Although the general SAT problem is NP-complete, advancements in solver algorithms and heuristics have meant that many industrial problems can be quickly and efficiently solved. Much of this progress has been made in the field of sequential SAT solvers; however, there have been significant recent contributions to the field of hardware SAT accelerators. This paper offers a short overview of the current state of SAT solvers in general and surveys recent contributions to hardware accelerated SAT solvers. This paper also aims to analyze the trends, challenges, and open questions facing reconfigurable SAT solvers in an extremely competitive application area.

[1]  Joao Marques-Silva,et al.  GRASP: A Search Algorithm for Propositional Satisfiability , 1999, IEEE Trans. Computers.

[2]  Prabhakar Goel,et al.  An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits , 1981, IEEE Transactions on Computers.

[3]  Tsutomu Maruyama,et al.  An FPGA solver for WSAT algorithms , 2005, International Conference on Field Programmable Logic and Applications, 2005..

[4]  Srinivas Patil,et al.  FPGA-based hardware acceleration for Boolean satisfiability , 2009, TODE.

[5]  Sharad Malik,et al.  Using configurable computing to accelerate Boolean satisfiability , 1999, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[6]  Niklas Sörensson,et al.  An Extensible SAT-solver , 2003, SAT.

[7]  Alessandro Dal Palù,et al.  CUD@SAT: SAT solving on GPUs , 2015, J. Exp. Theor. Artif. Intell..

[8]  Sharad Malik,et al.  Accelerating Boolean satisfiability with configurable hardware , 1998, Proceedings. IEEE Symposium on FPGAs for Custom Computing Machines (Cat. No.98TB100251).

[9]  Tsutomu Maruyama,et al.  FPGA acceleration of SAT/Max-SAT solving using variable-way cache , 2014, 2014 24th International Conference on Field Programmable Logic and Applications (FPL).

[10]  Alan Mishchenko,et al.  Applying Logic Synthesis for Speeding Up SAT , 2007, SAT.

[11]  Jason Thong,et al.  FPGA Acceleration of Decision-Based Problems using Heterogeneous Computing , 2014 .

[12]  Jinian Bian,et al.  SMPP: Generic SAT Solver over Reconfigurable Hardware Accelerator , 2012, 2012 IEEE 26th International Parallel and Distributed Processing Symposium Workshops & PhD Forum.

[13]  Armin Biere,et al.  Effective Preprocessing in SAT Through Variable and Clause Elimination , 2005, SAT.

[14]  Ashraf Salem,et al.  A reconfigurable, pipelined, conflict directed jumping search SAT solver , 2011, 2011 Design, Automation & Test in Europe.

[15]  Rolf Wanka,et al.  3-SAT on CUDA: Towards a massively parallel SAT solver , 2010, 2010 International Conference on High Performance Computing & Simulation.

[16]  Joao Marques-Silva Practical applications of Boolean Satisfiability , 2008, 2008 9th International Workshop on Discrete Event Systems.

[17]  Julian Stecklina,et al.  A short overview on modern parallel SAT-solvers , 2011, 2011 International Conference on Advanced Computer Science and Information Systems.

[18]  Fang Yu,et al.  Designing an Efficient Hardware Implication Accelerator for SAT Solving , 2008, SAT.

[19]  Iouliia Skliarova,et al.  A software/reconfigurable hardware SAT solver , 2004, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[20]  Satnam Singh,et al.  Relieving capacity limits on FPGA-based SAT-solvers , 2010, Formal Methods in Computer Aided Design.

[21]  Lakhdar Sais,et al.  ManySAT: a Parallel SAT Solver , 2009, J. Satisf. Boolean Model. Comput..

[22]  Nicola Nicolici,et al.  FPGA acceleration of enhanced boolean constraint propagation for SAT solvers , 2013, 2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[23]  Chanseok Oh Between SAT and UNSAT: The Fundamental Difference in CDCL SAT , 2015, SAT.

[24]  El Mostapha Aboulhamid,et al.  An Efficient Hardware Implementation of a SAT Problem Solver on FPGA , 2013, 2013 Euromicro Conference on Digital System Design.

[25]  Sharad Malik,et al.  Chaff: engineering an efficient SAT solver , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

[26]  Fang Yu,et al.  A practical reconfigurable hardware accelerator for boolean satisfiability solvers , 2008, 2008 45th ACM/IEEE Design Automation Conference.

[27]  Tsutomu Maruyama,et al.  An Approach for Solving Large SAT Problems on FPGA , 2010, TRETS.

[28]  Weiping Shi,et al.  Efficient, scalable hardware engine for Boolean satisfiability and unsatisfiable core extraction , 2008, IET Comput. Digit. Tech..

[29]  Vasco M. Manquinho,et al.  An overview of parallel SAT solving , 2012, Constraints.

[30]  Iouliia Skliarova,et al.  Reconfigurable hardware SAT solvers: a survey of systems , 2003, IEEE Transactions on Computers.

[31]  Marco Platzner,et al.  Acceleration of Satisfiability Algorithms by Reconfigurable Hardware , 1998, FPL.

[32]  Armin Biere,et al.  Cube and Conquer: Guiding CDCL SAT Solvers by Lookaheads , 2011, Haifa Verification Conference.

[33]  M. Watheq El-Kharashi,et al.  A Shift Register based Clause Evaluator for Reconfigurable SAT Solver , 2007, 2007 Design, Automation & Test in Europe Conference & Exhibition.

[34]  Donald W. Loveland,et al.  A machine program for theorem-proving , 2011, CACM.

[35]  Ashraf Salem,et al.  FPGA-Based SAT Solver , 2006, 2006 Canadian Conference on Electrical and Computer Engineering.