Lithography variability driven cell characterization and layout optimization for manufacturability

[1]  Alek C. Chen,et al.  Process capability comparison between LELE DPT and spacer for NAND flash 32nm and below , 2008, Lithography Asia.

[2]  Kanak Agarwal.  Frequency domain decomposition of layouts for double dipole lithography , 2010, Design Automation Conference.

[3]  Uwe Schroeder,et al.  Contact mask optimization and SRAF design , 2009, Advanced Lithography.

[4]  T. Sanuki,et al.  Variability aware modeling and characterization in standard cell in 45 nm CMOS with stress enhancement technique , 2008, 2008 Symposium on VLSI Technology.

[5]  Vincent Wiaux,et al.  Double pattern EDA solutions for 32nm HP and beyond , 2007, SPIE Advanced Lithography.

[6]  E. Schoell,et al.  Impact of photoresist composition and polymer chain length on line edge roughness probed with a stochastic simulator , 2007 .

[7]  Lars W. Liebmann,et al.  Resolution enhancement techniques in optical lithography: It's not just a mask problem , 2001, Photomask Japan.

[8]  A. Asenov,et al.  Intrinsic parameter fluctuations in decananometer MOSFETs introduced by gate line edge roughness , 2003 .

[9]  Edmund Y. Lam,et al.  Performance optimization for gridded-layout standard cells , 2004, SPIE Photomask Technology.

[10]  E. Gogolides,et al.  Line edge roughness and critical dimension variation: Fractal characterization and comparison using model functions , 2004 .

[11]  Evangelos Gogolides,et al.  Photoresist line-edge roughness analysis using scaling concepts , 2004 .

[12]  Jerry Liu,et al.  Advanced self-aligned double patterning development for sub-30-nm DRAM manufacturing , 2009, Advanced Lithography.

[13]  Chris A. Mack,et al.  Stochastic modeling in lithography: autocorrelation behavior of catalytic reaction–diffusion systems , 2009 .

[14]  Manfred Engelhardt,et al.  Impact of line edge roughness on the resistivity of nanometer-scale interconnects , 2004 .

[15]  Kun Yuan,et al.  A new graph-theoretic, multi-objective layout decomposition framework for Double Patterning Lithography , 2010, 2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC).

[16]  Dejan Markovic,et al.  Linear analysis of random process variability , 2008, ICCAD 2008.

[17]  Harry J. Levinson,et al.  Line edge roughness impact on critical dimension variation , 2007, SPIE Advanced Lithography.

[18]  K. Agarwal,et al.  A Test Structure for Assessing Individual Contact Resistance , 2009, 2009 IEEE International Conference on Microelectronic Test Structures.

[19]  G. Bonilla,et al.  On the contribution of line-edge roughness to intralevel TDDB lifetime in low-k dielectrics , 2009, 2009 IEEE International Reliability Physics Symposium.

[20]  Costas Spanos,et al.  Impact of gate line edge roughness on double-gate FinFET performance variability , 2008, SPIE Advanced Lithography.

[21]  Harry J. Levinson,et al.  The transfer of photoresist LER through etch , 2006, SPIE Advanced Lithography.

[22]  Evangelos Gogolides,et al.  Line-edge-roughness transfer during plasma etching: modeling approaches and comparison with experimental results , 2009 .

[23]  A. Asenov,et al.  Intrinsic threshold voltage fluctuations in decanano MOSFETs due to local oxide thickness variations , 2002 .

[24]  Sani R. Nassif,et al.  Characterizing Process Variation in Nanometer CMOS , 2007, 2007 44th ACM/IEEE Design Automation Conference.

[25]  Suman Datta,et al.  Impact of line-width roughness on Intel's 65-nm process devices , 2007, SPIE Advanced Lithography.

[26]  Costas J. Spanos,et al.  Comparative study of line width roughness (LWR) in next-generation lithography (NGL) processes , 2010, Advanced Lithography.

[27]  David Z. Pan,et al.  Electrical impact of line-edge roughness on sub-45-nm node standard cells , 2010 .

[28]  Andrew B. Kahng,et al.  Auxiliary pattern-based optical proximity correction for better printability, timing, and leakage control , 2008 .

[29]  Jae-Seok Yang,et al.  Overlay aware interconnect and timing variation modeling for double patterning technology , 2008, ICCAD 2008.

[30]  E. Nowak,et al.  Weibull breakdown characteristics and oxide thickness uniformity , 2000 .

[31]  David Z. Pan,et al.  Layout decomposition of self-aligned double patterning for 2D random logic patterning , 2011, Advanced Lithography.

[32]  David Z. Pan,et al.  On stress aware active area sizing, gate sizing, and repeater insertion , 2009, ISPD '09.

[33]  Vivek Raghavan,et al.  Model-assisted routing for improved lithography robustness , 2007, SPIE Advanced Lithography.

[34]  David Z. Pan,et al.  Flexible 2D layout decomposition framework for spacer-type double pattering lithography , 2011, 2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC).

[35]  Li-Da Huang,et al.  Optical proximity correction (OPC): friendly maze routing , 2004, DAC.

[36]  Yunfei Deng,et al.  Decomposition strategies for self-aligned double patterning , 2010, Advanced Lithography.

[37]  David Blaauw,et al.  Stress aware layout optimization , 2008, ISPD '08.

[38]  Wen-Chin Lee,et al.  Ultimate contact resistance scaling enabled by an accurate contact resistivity extraction methodology for sub-20 nm node , 2006, 2009 Symposium on VLSI Technology.

[39]  Yorick Trouiller,et al.  SRAF enhancement using inverse lithography for 32nm hole patterning and beyond , 2009, Photomask Technology.

[40]  Jae-Seok Yang,et al.  Layout aware line-edge roughness modeling and poly optimization for leakage minimization , 2011, 2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC).

[41]  Yi-Shiang Chang,et al.  Full area pattern decomposition of self-aligned double patterning for 30nm node NAND FLASH process , 2010, Advanced Lithography.

[42]  Andrew R. Neureuther,et al.  From poly line to transistor: building BSIM models for non-rectangular transistors , 2006, SPIE Advanced Lithography.

[43]  Karthik Balakrishnan,et al.  Measurement and analysis of contact plug resistance variability , 2009, 2009 IEEE Custom Integrated Circuits Conference.

[44]  Kun Yuan,et al.  ELIAD: Efficient lithography aware detailed router with compact post-OPC printability prediction , 2008, 2008 45th ACM/IEEE Design Automation Conference.

[45]  Michael C. Smayling,et al.  Low k1 logic design using gridded design rules , 2008, SPIE Advanced Lithography.

[46]  Liang Deng,et al.  Fast and Accurate OPC for Standard-Cell Layouts , 2007, 2007 Asia and South Pacific Design Automation Conference.

[47]  S. Narasimha,et al.  An integrated methodology for accurate extraction of S/D series resistance components in nanoscale MOSFETs , 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..

[48]  Kun Yuan,et al.  Layout Decomposition for Triple Patterning Lithography , 2015, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[49]  Rajendran Panda,et al.  Electrical impact of line-edge roughness on sub-45nm node standard cell , 2009, Advanced Lithography.

[50]  David Laidler,et al.  Overlay metrology for double patterning processes , 2009, Advanced Lithography.

[51]  G. Gallatin,et al.  Residual speckle in a lithographic illumination system , 2009 .

[52]  Yu Cao,et al.  Design rule optimization of regular layout for leakage reduction in nanoscale design , 2008, 2008 Asia and South Pacific Design Automation Conference.

[53]  Andrzej J. Strojwas,et al.  Design methodology for IC manufacturability based on regular logic-bricks , 2005, Proceedings. 42nd Design Automation Conference, 2005..

[54]  Kurt Keutzer,et al.  Impact of spatial intrachip gate length variability on theperformance of high-speed digital circuits , 2002, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[55]  David Z. Pan,et al.  RADAR: RET-aware detailed routing using fast lithography simulations , 2005, Proceedings. 42nd Design Automation Conference, 2005..

[56]  John Arnold,et al.  Integration of EUV lithography in the fabrication of 22-nm node devices , 2009, Advanced Lithography.

[57]  Philippe Hurat,et al.  Layout printability optimization using a silicon simulation methodology , 2004, International Symposium on Signals, Circuits and Systems. Proceedings, SCS 2003. (Cat. No.03EX720).

[58]  Peng Yu,et al.  A Unified Non-Rectangular Device and Circuit Simulation Model for Timing and Power , 2006, 2006 IEEE/ACM International Conference on Computer Aided Design.

[59]  David Z. Pan,et al.  Modeling and characterization of contact-edge roughness for minimizing design and manufacturing variations , 2010 .

[60]  Thomas Klimpel,et al.  Analysis of topography effects on lithographic performance in double patterning applications , 2009, Advanced Lithography.

[61]  Yunfei Deng,et al.  Modeling and characterization of contact-edge roughness for minimizing design and manufacturing variations in 32-nm node standard cell , 2010, Advanced Lithography.

[62]  Kuen-Yu Tsai,et al.  A new method to improve accuracy of leakage current estimation for transistors with non-rectangular gates due to sub-wavelength lithography effects , 2008, ICCAD 2008.

[63]  David Z. Pan,et al.  Total sensitivity based dfm optimization of standard library cells , 2010, ISPD '10.

[64]  Yao-Wen Chang,et al.  Multilevel Full-Chip Gridless Routing With Applications to Optical-Proximity Correction , 2007, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[65]  Andrew B. Kahng,et al.  Timing Yield-Aware Color Reassignment and Detailed Placement Perturbation for Bimodal CD Distribution in Double Patterning Lithography , 2010, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[66]  Yu Cao,et al.  Statistical modeling and simulation of threshold variation under dopant fluctuations and line-edge roughness , 2008, 2008 45th ACM/IEEE Design Automation Conference.

[67]  Jiang Hu,et al.  Standard cell characterization considering lithography induced variations , 2006, 2006 43rd ACM/IEEE Design Automation Conference.

[68]  Andreas Erdmann,et al.  A comprehensive resist model for the prediction of line-edge roughness material and process dependencies in optical lithography , 2008, SPIE Advanced Lithography.

[69]  Stephen P. Boyd,et al.  Convex Optimization , 2004, Algorithms and Theory of Computation Handbook.

[70]  Lars W. Liebmann,et al.  OPC simplification and mask cost reduction using regular design fabrics , 2009, Advanced Lithography.

[71]  Yi-Kan Cheng,et al.  DFM viewpoints of cell-level layout assessments and indications for concurrent layout optimization , 2008, Photomask Technology.

[72]  Lawrence T. Pileggi,et al.  Design Methodology of Regular Logic Bricks for Robust Integrated Circuits , 2006, 2006 International Conference on Computer Design.

[73]  C. Mack.  Fundamental principles of optical lithography , 2007 .

[74]  Ting-Chi Wang,et al.  Maze routing with OPC consideration , 2005, Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005..

[75]  Lars W. Liebmann,et al.  Taming the final frontier of optical lithography: design for sub-resolution patterning , 2010, Advanced Lithography.

[76]  Geert Vandenberghe,et al.  Hyper-NA imaging of 45nm node random CH layouts using inverse lithography , 2008, SPIE Advanced Lithography.

[77]  Kun Yuan,et al.  Double Patterning Layout Decomposition for Simultaneous Conflict and Stitch Minimization , 2010, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[78]  Byoung-Ho Lee,et al.  Experimental study of contact edge roughness on sub-100 nm various circular shapes , 2005, SPIE Advanced Lithography.

[79]  Ching-Te Chuang,et al.  Random Dopant Fluctuation in Limited-Width FinFET Technologies , 2007, IEEE Transactions on Electron Devices.

[80]  Kenji Yamazaki,et al.  Influence of edge roughness in resist patterns on etched patterns , 1998 .

[81]  Puneet Gupta,et al.  Investigation of diffusion rounding for post-lithography analysis , 2008, 2008 Asia and South Pacific Design Automation Conference.

[82]  Thomas Schmoeller,et al.  Split, overlap/stitching, and process design for double patterning considering local reflectivity variation by using rigorous 3D wafer-topography/lithography simulation , 2009, Advanced Lithography.

[83]  Philippe Hurat,et al.  Implementation of silicon-validated variability analysis and optimization for standard cell libraries , 2008, SPIE Advanced Lithography.

[84]  David Z. Pan,et al.  Double patterning technology friendly detailed routing , 2008, ICCAD 2008.