论文信息 - An Equivalence Decision Problem in Systolic Array Verification

An Equivalence Decision Problem in Systolic Array Verification

Verification of linear algebra and signal processing systolic circuit families is reduced to a zero equivalence problem for expressions containing indefinite summation. This problem is solved using a linear case of algebraic decomposition and reducing it to the zero equivalence problem for a finite set of multivariate polynomials.

Parosh Aziz Abdulla | Stefan Arnborg

[1] Jiawei Hong,et al. Proving by example and gap theorems , 1986, 27th Annual Symposium on Foundations of Computer Science (sfcs 1986).

[2] Dan I. Moldovan,et al. On the Analysis and Synthesis of VLSI Algorithms , 1982, IEEE Transactions on Computers.

[3] Martin D. Davis. Hilbert's Tenth Problem is Unsolvable , 1973 .

[4] Björn Lisper. Synthesizing Synchronous Systems by Static Scheduling in Space-Time , 1989, Lecture Notes in Computer Science.

[5] George E. Collins,et al. Cylindrical Algebraic Decomposition I: The Basic Algorithm , 1984, SIAM J. Comput..

[6] Jeffrey D Ullma. Computational Aspects of VLSI , 1984 .

[7] George E. Collins,et al. Cylindrical Algebraic Decomposition II: An Adjacency Algorithm for the Plane , 1984, SIAM J. Comput..

[8] Jacob T. Schwartz,et al. Fast Probabilistic Algorithms for Verification of Polynomial Identities , 1980, J. ACM.

[9] M. Gordon. HOL: A Proof Generating System for Higher-Order Logic , 1988 .

[10] Gaston H. Gonnet,et al. Determining equivalence of expressions in random polynomial time , 1984, STOC '84.