Effect of Damage in Source and Drain on the Endurance of a 65-nm-Node NOR Flash Memory

On 12-in wafers of 65-nm-node floating gate NOR flash memory, charge pumping measurements show that compared to those on the edge dies (type A), the devices on the central dies (type B) have more severe damage in the source (S) and drain (D) regions. In type-B devices, the worse damage is due to the generation of interface traps in the S/channel overlapping region and the generation of bulk traps in the S and D junction region. In type-A devices, the damage is much weaker. The generation of interface traps is observed in the S/channel overlapping region. However, it is hardly measurable on the D side. The endurance characteristics have been measured in these two kinds of devices under the channel hot electron program and Fowler-Nordheim erase. In type-B devices, after program/erase cycling the memory window closure is more serious and the junction leakage also degrades greatly with the generation of a lot of bulk traps at S and D regions. The damage in fresh devices is suggested to be due to the plasma etching processes.

[1]  A. Ghetti,et al.  A 65nm NOR flash technology with 0.042/spl mu/m/sup 2/ cell size for high performance multilevel application , 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..

[2]  James H. Stathis,et al.  Interface states induced by the presence of trapped holes near the silicon–silicon‐dioxide interface , 1995 .

[3]  M. Wei,et al.  A Scalable Self-Aligned Contact NOR Flash Technology , 2007, 2007 IEEE Symposium on VLSI Technology.

[4]  G. Groeseneken,et al.  A reliable approach to charge-pumping measurements in MOS transistors , 1984, IEEE Transactions on Electron Devices.

[5]  Roberto Bez,et al.  Failure mechanisms of flash cell in program/erase cycling , 1994, Proceedings of 1994 IEEE International Electron Devices Meeting.

[6]  N. Ito,et al.  A Novel Program and Read Architecture for Contact-Less Virtual Ground NOR Flash Memory for High Density Application , 2006, 2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers..

[7]  B. Eitan,et al.  Subthreshold slope degradation model for localized-charge-trapping based non-volatile memory devices , 2003 .

[8]  Joe Brewer,et al.  Nonvolatile memory technologies with emphasis on flash , 2007 .

[9]  Piero Olivo,et al.  Flash memory cells-an overview , 1997, Proc. IEEE.

[10]  Guoqiao Tao,et al.  A Quantitative Study of Endurance Characteristics and Its Temperature Dependance of Embedded Flash Memories With 2T-FNFN nor Device Architecture , 2007, IEEE Transactions on Device and Materials Reliability.

[11]  Tibor Grasser,et al.  An analytical approach for physical modeling of hot-carrier induced degradation , 2011, Microelectron. Reliab..

[12]  G. Groeseneken,et al.  On the geometric component of charge-pumping current in MOSFETs , 1993, IEEE Electron Device Letters.

[13]  M. Wei,et al.  Flash ETOX/spl trade/ virtual ground architecture: a future scaling direction , 2005, Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005..

[14]  J. S. Huang,et al.  A Highly Punchthrough-Immune Array Architecture and Program Method for Floating-Gate NOR-Type Nonvolatile Memory , 2011, IEEE Transactions on Electron Devices.