Exploring system-on-panel integration for next-generation display applications

Following the advent of the digital multi-media era and the popularity of the internet, high-resolution flat-panel displays are becoming the central feature of many consumer products. This dissertation is to explore the challenges and opportunities of system-on-panel (SoP) integration for next-generation high-performance multifunctional flat-panel display products. SoP integration, which aims to mount a display screen and its analogue and digital display driver circuits as well as other high-level function integrated circuits (ICs) on the same glass substrate, will help realize the implementation of high-density, multifunctional, compact display products, and also lead to a substantial savings in costs by shortening the display manufacturing and inspection processes while maintaining a level of high reliability. This dissertation makes contributions on three aspects. Firstly, the dissertation explores the device structure and related design implications for the continuous down-scaling of polycrystalline silicon (poly-Si) thin-film transistors, which is the most promising candidate for building ICs in SoP integration. The thick source/drain nanometre-scale ultra-thin channel poly-Si transistors are demonstrated with desirable performance and ultra-scaling capability in this work. The further analysis by numerical device simulation gives the implications for optimal design of poly-Si TFTs down to sub-100-nm regime. The second contribution is to design and analyze the pixel circuits for the self-emissive type display technologies, i.e. organic light emission diode (OLED) and carbon nanotube (CNT) based field emission displays (FEDs). The merits and related design issues of the switch-current pixel circuits are fully studied. And to integrate the light element devices into SPICE circuit simulations, a simple and effective macro-modelling approach is proposed. Finally, this dissertation also investigates the electro-thermal effects in SoP integration. The analysis results show the much more severe electro-thermal effects in SoP integration compared to that of conventional bulk CMOS and SOI technologies. Possible heating removing and management methods are given for the progress of reliable SoP integration.

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