Dynamic fault detection in digital systems using dynamic voltage scaling and multi-temperature schemes

Detection of physical defects (or transient faults) in nanometer products is very challenging. Parametric test, using variable power supply voltage, clock frequency and temperature can be rewarding. However, their impact on digital system performance needs to be evaluated. In this paper, a novel semi-empirical analytical model to compute, at logic level, the impact of power supply voltage variations (DeltaVDD) and/or of temperature variations (DeltaT) on speed response of a digital module is proposed. The model allows low-cost fault simulation. Moreover, it is shown that delay variation can be emulated either by a DeltaVDDi or a DeltaTj variation. The on-chip availability of multiple VDD values in products with DVS (dynamic voltage scaling) opens opportunities for novel BIST techniques. A new DVS-based BIST approach is proposed and its ability to detect and diagnose resistive open defects is ascertained

[1]  Alan Jay Smith,et al.  Improving dynamic voltage scaling algorithms with PACE , 2001, SIGMETRICS '01.

[2]  David Blaauw,et al.  Theoretical and practical limits of dynamic voltage scaling , 2004, Proceedings. 41st Design Automation Conference, 2004..

[3]  Kwang-Ting Cheng,et al.  Enhancing diagnosis resolution for delay defects based upon statistical timing and statistical fault models , 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).

[4]  Krishnendu Chakrabarty,et al.  Thermal-Safe Test Scheduling for Core-Based System-on-Chip Integrated Circuits , 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[5]  Krisztian Flautner,et al.  A Combined Hardware-Software Approach for Low-Power SoCs: Applying Adaptive Voltage Scaling and Intelligent Energy Management Software , 2003 .

[6]  Ying Zhang,et al.  Dynamic adaptation for fault tolerance and power management in embedded real-time systems , 2004, TECS.

[7]  Ying Zhang,et al.  Energy-aware deterministic fault tolerance in distributed real-time embedded systems , 2004, Proceedings. 41st Design Automation Conference, 2004..

[8]  R. Alves.  Dynamic Fault Test and Diagnosis in Digital Systems Using Multiple Clock Schemes and Multi-VDD Test , 2005 .

[9]  Dragan Maksimovic,et al.  Closed-loop adaptive voltage scaling controller for standard-cell ASICs , 2002, ISLPED '02.

[10]  J. P. Teixeira,et al.  Modeling of Power Supply Transients for EMI Compliance in Digital Systems , 2004 .

[11]  Trevor Mudge,et al.  Razor: a low-power pipeline based on circuit-level timing speculation , 2003, Proceedings. 36th Annual IEEE/ACM International Symposium on Microarchitecture, 2003. MICRO-36..

[12]  Thomas D. Burd,et al.  The simulation and evaluation of dynamic voltage scaling algorithms , 1998, Proceedings. 1998 International Symposium on Low Power Electronics and Design (IEEE Cat. No.98TH8379).

[13]  João Paulo Teixeira,et al.  Fault Modeling and Simulation of Power Supply Voltage Transients in Digital Systems on a Chip , 2005, J. Electron. Test..