Chip-to-chip interconnection, based on wireless communication by capacitive coupling was investigated. This innovative approach will considerably reduce the pitch of the pin and strongly help in the implementation of a dense network of interconnects, while improving inter-chip bandwidth and power dissipation. The 3D integration technology based on aligned wafer-to-wafer direct bonding technique was implemented for IC capacitive interconnection realization. The capacitive structures are created by facing two wafers with symmetrical IC chips bearing at last level a two-dimensional array of metal arms covered by a dielectric layer. Communication take place by capacitive coupling using capacitors created at location in the aligned micro-array. The capacitance dielectric thickness was monitored during the wafer bonding. Specific wafer process flow and especially precise circuit alignment were applied; in order to create between the bonded chips the capacitive interconnect arrays. After bonding, one wafer was thinned down, and I/O via were opened though the piled up remaining silicon and the two bonded stacks of CMOS structures. That elaborated structure was then ready for wire bonding. Electrical characterization tests are performed and the first functional testing gives very good performances in high-speed communication between the stacked chips.