Impedance profile of a commercial power grid and test system

An impedance profile of a commercial power grid and a tester power distribution system is developed in this paper. The profile is used to identify the measurable frequency range of the power supply transient signals generated by a chip. Several resistance-capacitance (RC) models of the power grid are analyzed to determine the impact of each capacitance type. The impedance profile of a C4-based production testing environment is then developed. The impedance profile of the combined probe card and the power grid RC models illustrates the range of frequencies that are measurable at the supply ports of the chip-under-test (CUT). The results suggest that it is possible to measure the important frequency components of a chip's power supply transients in a production test environment for use in fault detection and localization procedures. Conventional testing methods are challenged by changing circuit sensitivities and emerging defect mechanisms resulting from the use of new fabrication materials in very deep submicron processes [1]. For example, the change from a subtractive aluminum process to damascene Cu may lead to more particle-related blocked-etch resistive opens. Technology scaling also increases the probability of resis-tive vias caused by incomplete etch. The additional delays introduced by these types of resistive defects in combination with increased circuit sensitivity due to shorter clock cycles, reduced timing slack, crosstalk and PWR/GND bounce increase the likelihood of random defects causing delay fails. Similarly, hardware-based fault localization is challenged by increases in chip complexity as well as additional interconnection levels and the limitations on the spatial resolution of imaging technology. The increase in difficulty and cost of performing hardware physical failure analysis is likely to move it into a sampling/verification role. These trends continue to increase the importance of developing alternative software-based fault localization procedures. We believe that power supply testing methods are well aligned with these needs and others as described in the International Technology Roadmap for Semiconductors. In our previous work, a testing method is presented for fault detection that uses correlation analysis of multiple simultaneously measured power supply transient signals [2]. The transients at each of the supply ports of a chip-under-test (CUT) are cross-correlated to reduce the adverse effects of process variations on fault detection resolution. The multiple supply port measurements are analyzed for the regional signal anomalies introduced by defects. The regression analysis technique that we propose in [3] is able to detect anomalies in the ratios of the waveform …

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