Schedule-clock-tree routing for semi-synchronous circuits

It is known that the clock-period can be shorter than the maximum of signal-delays between registers if the clock arrival time to each register is properly scheduled. The algorithm to design an optimal clock-schedule was given. In this paper, we propose a clock-tree routing algorithm that realizes a given clock-schedule using the Elmore-delay model. Following the deferred-merge-embedding (DME) framework, the algorithm generates a topology of the clock-tree and simultaneously determines the locations and sizes of intermediate buffers. The experimental results showed that this method constructs a clocktree with moderate wire length for a random layout of scheduled registers. Notably, the required wire length for a gentle layout of scheduled registers was shown to be almost equal to that of zero-skew clock-trees. key words: clock-tree, clock-scheduling, semi-synchronous circuit, deferred-merge embedding

[1]  E. Friedman,et al.  Topological design of clock distribution networks based on non-zero clock skew specifications , 1993, Proceedings of 36th Midwest Symposium on Circuits and Systems.

[2]  Jan-Ming Ho,et al.  Zero skew clock routing with minimum wirelength , 1992 .

[3]  Maciej J. Ciesielski,et al.  Placement for clock period minimization with multiple wave propagation , 1991, 28th ACM/IEEE Design Automation Conference.

[4]  R.-S. Tsay,et al.  Exact zero skew , 1991, 1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers.

[5]  M. Edahiro,et al.  Minimum skew and minimum path length routing in VLSI layout design , 1991 .

[6]  Eby G. Friedman,et al.  Minimizing power dissipation in non-zero skew-based clock distribution networks , 1995, Proceedings of ISCAS'95 - International Symposium on Circuits and Systems.

[7]  Atsushi Takahashi,et al.  Clock-tree routing realizing a clock-schedule for semi-synchronous circuits , 1997, 1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD).

[8]  Atsushi Takahashi,et al.  Performance and reliability driven clock scheduling of sequential logic circuits , 1997, Proceedings of ASP-DAC '97: Asia and South Pacific Design Automation Conference.

[9]  Yoji Kajitani,et al.  Clock-Routing Driven Layout Methodology for Semi-Synchronous Circuit Design , 1997 .

[10]  Eby G. Friedman,et al.  Circuit synthesis of clock distribution networks based on non-zero clock skew , 1994, Proceedings of IEEE International Symposium on Circuits and Systems - ISCAS '94.

[11]  Andrew B. Kahng,et al.  Zero-skew clock routing trees with minimum wirelength , 1992, [1992] Proceedings. Fifth Annual IEEE International ASIC Conference and Exhibit.

[12]  John P. Fishburn,et al.  Clock Skew Optimization , 1990, IEEE Trans. Computers.

[13]  Sachin S. Sapatnekar,et al.  A graph-theoretic approach to clock skew optimization , 1994, Proceedings of IEEE International Symposium on Circuits and Systems - ISCAS '94.

[14]  Masato Edahiro,et al.  A Clustering-Based Optimization Algorithm in Zero-Skew Routings , 1993, 30th ACM/IEEE Design Automation Conference.

[15]  Jan-Ming Ho,et al.  Zero skew clock net routing , 1992, [1992] Proceedings 29th ACM/IEEE Design Automation Conference.

[16]  Malgorzata Marek-Sadowska Ashok Vittal.  Power Optimal Buffered Clock Tree Design , 1995, 32nd Design Automation Conference.

[17]  Wayne Wei-Ming Dai,et al.  Useful-skew clock routing with gate sizing for low power design , 1996, DAC '96.

[18]  A. Kahng,et al.  Bounded-skew clock and Steiner routing under Elmore delay , 1995, Proceedings of IEEE International Conference on Computer Aided Design (ICCAD).

[19]  D. Huang.  On the bounded-skew routing tree problem , 1995, DAC 1995.

[20]  Jason Cong,et al.  Minimum-cost bounded-skew clock routing , 1995, Proceedings of ISCAS'95 - International Symposium on Circuits and Systems.

[21]  Thomas G. Szymanski,et al.  Computing optimal clock schedules , 1992, [1992] Proceedings 29th ACM/IEEE Design Automation Conference.

[22]  Wayne W.-M. Dai,et al.  Jitter-tolerant clock routing in two-phase synchronous systems , 1996, ICCAD 1996.

[23]  Jason Cong,et al.  Performance optimization of VLSI interconnect layout , 1996, Integr..

[24]  Martin D. F. Wong,et al.  An algorithm for zero-skew clock tree routing with buffer insertion , 1996, Proceedings ED&TC European Design and Test Conference.