Self-Timed Scheduling Analysis for Real-Time Applications
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[1] E.A. Lee,et al. Synchronous data flow , 1987, Proceedings of the IEEE.
[2] C. Leake. Synchronization and Linearity: An Algebra for Discrete Event Systems , 1994 .
[3] Guang R. Gao,et al. Minimizing memory requirements in rate-optimal schedules , 1994, Proceedings of IEEE International Conference on Application Specific Array Processors (ASSAP'94).
[4] Guang R. Gao,et al. A novel framework for multi-rate scheduling in DSP applications , 1993, Proceedings of International Conference on Application Specific Array Processors (ASAP '93).
[5] Ali Dasdan,et al. Experimental analysis of the fastest optimum cycle ratio and mean algorithms , 2004, TODE.
[6] Kees G. W. Goossens,et al. A unified approach to constrained mapping and routing on network-on-chip architectures , 2005, 2005 Third IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS'05).
[7] Ajm Arno Moonen,et al. Timing analysis model for network based multiprocessor systems. , 2004 .
[8] R. K. Shyamasundar,et al. Introduction to algorithms , 1996 .
[9] Raymond Reiter,et al. Scheduling Parallel Computations , 1968, J. ACM.
[10] Giorgio Buttazzo,et al. Hard Real-Time Computing Systems: Predictable Scheduling Algorithms and Applications , 1997 .
[11] Sander Stuijk,et al. Dataflow Analysis for Real-Time Embedded Multiprocessor System Design , 2005 .
[12] Kees Goossens,et al. AEthereal network on chip: concepts, architectures, and implementations , 2005, IEEE Design & Test of Computers.
[13] Edward A. Lee,et al. Static Scheduling of Synchronous Data Flow Programs for Digital Signal Processing , 1989, IEEE Transactions on Computers.
[14] Orlando Moreira,et al. Multiprocessor resource allocation for hard-real-time streaming with a dynamic job-mix , 2005, 11th IEEE Real Time and Embedded Technology and Applications Symposium.
[15] Steve Goddard,et al. Managing Latency and Buffer Requirements in Processing Graph Chains , 2001, Comput. J..
[16] Ronald L. Rivest,et al. Introduction to Algorithms , 1990 .
[17] Marco J. G. Bekooij,et al. A multi-core architecture for incCar digital entertainment , 2005 .
[18] Sander Stuijk,et al. Throughput Analysis of Synchronous Data Flow Graphs , 2006, Sixth International Conference on Application of Concurrency to System Design (ACSD'06).
[19] Orlando Moreira,et al. Online resource management in a multiprocessor with a network-on-chip , 2007, SAC '07.
[20] Shuvra S. Bhattacharyya,et al. Intermediate Representations for Design Automation of Multiprocessor DSP Systems , 2002, Des. Autom. Embed. Syst..
[21] Shuvra S. Bhattacharyya,et al. Embedded Multiprocessors: Scheduling and Synchronization , 2000 .
[22] Twan Basten,et al. Task-level timing models for guaranteed performance in multiprocessor networks-on-chip , 2003, CASES '03.
[23] Rolf Ernst,et al. Performance analysis for complex embedded applications , 2005, Int. J. Embed. Syst..