Tune-Up Friendly Fast Simulated Annealer for VLSI Analog Module Placement

Abstract As an efficient stochastic optimization methodology, simulated annealing (SA) is widely used in the area of very large-scale integration (VLSI) electronic design automation. However, a lot of effort is normally required to tune up SA parameters when being used for distinct applications. In this paper we propose an easy tune-up very fast simulated re-annealing algorithm to solve the problem of analog module placement. Compared to the classical Boltzmann or Cauchy annealing schemes, our method can converge to the global minimum statistically exponentially faster. Moreover, we deploy a re-annealing process to conduct adaptive control on the cooling schedules. Thus, the algorithm tune-up for the analog module placement problem is significantly relieved. Besides the theoretical analysis, our experiments show the proposed algorithm is superior over the other SA derivatives and is able to generate high-quality placement results with significantly less central processing unit (CPU) time.