A pipelined VLSI architecture for Sample Adaptive Offset (SAO) filter and deblocking filter of HEVC

This paper present a high throughput design for Sample Adaptive offset (SAO) filter and deblocking filter used in an HEVC decoder. A five-stage pipelined architecture is proposed to support both SAO filter and deblocking filter on a 32 × 32 pixel block basis. Deblocking filter and SAO filter can work simultaneously in consecutive pipeline stages. The on-chip SRAM can also be shared by deblocking filter and SAO filter. Coupled with the novel filter order, an interlaced SRAM memory mapping scheme is proposed to increase the throughput for deblocking filter. The experimental results show that our design can support 4K × 2K@60 fps (4096 × 2304) HEVC video sequence at the working frequency of only 60.8 MHz.