Single-ISA heterogeneous multi-core architectures for multithreaded workload performance
暂无分享,去创建一个
Norman P. Jouppi | Dean M. Tullsen | Rakesh Kumar | Parthasarathy Ranganathan | Keith I. Farkas | D. Tullsen | N. Jouppi | P. Ranganathan | K. Farkas | Rakesh Kumar | Parthasarathy Ranganathan | Rakesh Kumar | Keith I. Farkas
[1] David A. Patterson,et al. Computer Architecture: A Quantitative Approach , 1969 .
[2] Norman P. Jouppi,et al. Computer technology and architecture: an evolving interaction , 1991, Computer.
[3] David W. Wall,et al. Limits of instruction-level parallelism , 1991, ASPLOS IV.
[4] Dean M. Tullsen,et al. Simultaneous multithreading: Maximizing on-chip parallelism , 1995, Proceedings 22nd Annual International Symposium on Computer Architecture.
[5] Jack L. Lo,et al. Exploiting Choice: Instruction Fetch and Issue on an Implementable Simultaneous Multithreading Processor , 1996, 23rd Annual International Symposium on Computer Architecture (ISCA'96).
[6] Soonhoi Ha,et al. A Static Scheduling Heuristic for Heterogeneous Processors , 1996, Euro-Par, Vol. II.
[7] Dean M. Tullsen,et al. Fellowship - Simulation And Modeling Of A Simultaneous Multithreading Processor , 1996, Int. CMG Conference.
[8] Kunle Olukotun,et al. A Single-Chip Multiprocessor , 1997, Computer.
[9] G.E. Moore,et al. Cramming More Components Onto Integrated Circuits , 1998, Proceedings of the IEEE.
[10] Salim Hariri,et al. Task scheduling algorithms for heterogeneous processors , 1999, Proceedings. Eighth Heterogeneous Computing Workshop (HCW'99).
[11] R.H. Dennard,et al. Design Of Ion-implanted MOSFET's with Very Small Physical Dimensions , 1974, Proceedings of the IEEE.
[12] Luiz André Barroso,et al. Piranha: a scalable architecture based on single-chip multiprocessing , 2000, Proceedings of 27th International Symposium on Computer Architecture (IEEE Cat. No.RS00201).
[13] Dean M. Tullsen,et al. Symbiotic jobscheduling for a simultaneous mutlithreading processor , 2000, SIGP.
[14] Renato J. O. Figueiredo,et al. Impact of heterogeneity on DSM performance , 2000, Proceedings Sixth International Symposium on High-Performance Computer Architecture. HPCA-6 (Cat. No.PR00550).
[15] Yves Robert,et al. The master-slave paradigm with heterogeneous processors , 2001, Proceedings 42nd IEEE Symposium on Foundations of Computer Science.
[16] Dean M. Tullsen,et al. Handling long-latency loads in a simultaneous multithreading processor , 2001, MICRO.
[17] Jean-Luc Gaudiot,et al. SMT Layout Overhead and Scalability , 2002, IEEE Trans. Parallel Distributed Syst..
[18] Matthew Mattina,et al. Tarantula: a vector extension to the alpha architecture , 2002, Proceedings 29th Annual International Symposium on Computer Architecture.
[19] Norman P. Jouppi,et al. Processor Power Reduction Via Single-ISA Heterogeneous Multi-Core Architectures , 2003, IEEE Computer Architecture Letters.
[20] Brad Calder,et al. Discovering and Exploiting Program Phases , 2003, IEEE Micro.
[21] Single-ISA Heterogeneous Multi-Core Architectures: The Potential for Processor Power Reduction , 2003, MICRO.