A low-power CAM using a 12-transistor design cell

A low-power CAM design using a 12-transistor cell is proposed. The CAM cell is based on the conventional 6T cross- coupled inverters used for storing data with an addition of two NMOS transistors for reading out. In addition, the CAM has another four transistors for mask comparison operation through classical pre-charge operation. The read-out port exploits a pre- charge reading mechanism in order to alleviate the drawback of power consumption generated from sensing amplifiers and all other related synchronization circuits which are structured in every column in the memory. Thus, the read and match features can have concurrent operations. An experimental CAM structure of storage size 64-bit x 128-bit is designed using 0.18- μm CMOS single poly and three layers of metals measuring a cell die area of 24.4375 μm2 and a total silicon area of 0.269192 mm2. The circuit works up to 200 MHz in simulation with total power consumption of 0.016 W at 1.8-V supply voltage

[1]  Hisatada Miyatake,et al.  A design for high-speed low-power CMOS fully parallel content-addressable memory macros , 2001 .

[2]  J.G. Delgado-Frias,et al.  A dynamic content addressable memory using a 4-transistor cell , 1999, Proceedings of the Third International Workshop on Design of Mixed-Mode Integrated Circuits and Applications (Cat. No.99EX303).

[3]  Anna W. Topol,et al.  Stable SRAM cell design for the 32 nm node and beyond , 2005, Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005..

[4]  Charles A. Zukowski,et al.  VLSI implementation of routing tables: tries and CAMs , 1991, IEEE INFCOM '91. The conference on Computer Communications. Tenth Annual Joint Comference of the IEEE Computer and Communications Societies Proceedings.

[5]  Narayanan Vijaykrishnan,et al.  A novel low power CAM design , 2001, Proceedings 14th Annual IEEE International ASIC/SOC Conference (IEEE Cat. No.01TH8558).

[6]  C. G. Sodini,et al.  A ternary content addressable search engine , 1989 .

[7]  J. C. Chang,et al.  Design for low-power, low-cost, and high-reliability precomputation-based content-addressable memory , 2002, Asia-Pacific Conference on Circuits and Systems.

[8]  C.-Y. Lee,et al.  High-throughput data compressor designs using content addressable memory , 1995 .

[9]  Kuo-Hsing Cheng,et al.  Design of low-power content-addressable memory cell , 2003, 2003 46th Midwest Symposium on Circuits and Systems.

[10]  Sethuraman Panchanathan,et al.  A content-addressable memory architecture for image coding using vector quantization , 1991, IEEE Trans. Signal Process..

[11]  H. Hara,et al.  A 1-Mb 2-Tr/b nonvolatile CAM based on flash memory technologies , 1996 .

[12]  Vladimir Stojanovic,et al.  Comparative analysis of master-slave latches and flip-flops for high-performance and low-power systems , 1999, IEEE J. Solid State Circuits.

[13]  K. Takeda,et al.  A read-static-noise-margin-free SRAM cell for low-V/sub dd/ and high-speed applications , 2005, ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005..