A Predictable Multiprocessor Design Flow for Streaming Applications with Dynamic Behaviour

The design of new embedded systems is getting more and more complex as more functionality is integrated into these systems. To deal with the design complexity, a predictable design flow is needed. The result should be a system that guarantees that an application can perform its own tasks within strict timing deadlines, independent of other applications running on the system. Synchronous Dataflow Graphs (SDFGs) provide predictability and are often used to model time-constrained streaming applications that are mapped onto a multiprocessor platform. However, the model abstracts from the dynamic application behaviour which may lead to a large overestimation of its resource requirements. We present a design flow that takes the dynamic behaviour of applications into account when mapping them onto a multiprocessor platform. The design flow provides throughput guarantees for each application independent of the other applications while taking into account the available processing capacity, memory and communication bandwidth. The design flow generates a set of mappings that provide a trade-off in their resource usage. This trade-off can be used by a run-time mechanism to adapt the mapping in different use-cases to the available resource. The experimental results show that our design flow reduces the resource requirements of an MPEG-4 decoder by 66% compared to a state-of-the-art design flow based on SDFGs.

[1]  Krzysztof Kuchcinski,et al.  Constraints-driven scheduling and resource assignment , 2003, TODE.

[2]  Xue Liu,et al.  Efficient SAT-Based Mapping and Scheduling of Homogeneous Synchronous Dataflow Graphs for Throughput Optimization , 2008, 2008 Real-Time Systems Symposium.

[3]  Ajm Arno Moonen,et al.  Timing analysis model for network based multiprocessor systems. , 2004 .

[4]  H. Corporaal,et al.  Fast Multi-Dimension Multi-Choice Knapsack Heuristic for MP-SoC Run-Time Management , 2006, 2006 International Symposium on System-on-Chip.

[5]  Sander Stuijk,et al.  A scenario-aware data flow model for combined long-run average and worst-case performance analysis , 2006, Fourth ACM and IEEE International Conference on Formal Methods and Models for Co-Design, 2006. MEMOCODE '06. Proceedings..

[6]  Sander Stuijk,et al.  A parameterized compositional multi-dimensional multiple-choice knapsack heuristic for CMP run-time management , 2009, 2009 46th ACM/IEEE Design Automation Conference.

[7]  Orlando Moreira,et al.  Multiprocessor resource allocation for hard-real-time streaming with a dynamic job-mix , 2005, 11th IEEE Real Time and Embedded Technology and Applications Symposium.

[8]  Hugh Garraway Parallel Computer Architecture: A Hardware/Software Approach , 1999, IEEE Concurrency.

[9]  Orlando Moreira,et al.  Scheduling multiple independent hard-real-time jobs on a heterogeneous multiprocessor , 2007, EMSOFT '07.

[10]  Soonhoi Ha,et al.  PeaCE: A hardware-software codesign environment for multimedia embedded systems , 2008, TODE.

[11]  Soheil Ghiasi,et al.  Throughput-driven synthesis of embedded software for pipelined execution on multicore architectures , 2009, TECS.

[12]  Luca Benini,et al.  Throughput Constraint for Synchronous Data Flow Graphs , 2009, CPAIOR.

[13]  Peter van der Stok Dynamic and Robust Streaming in and between Connected Consumer-Electronic Devices , 2011 .

[14]  Sander Stuijk,et al.  Throughput Analysis of Synchronous Data Flow Graphs , 2006, Sixth International Conference on Application of Concurrency to System Design (ACSD'06).

[15]  Jacek Blazewicz,et al.  Scheduling Dependent Tasks with Different Arrival Times to Meet Deadlines , 1976, Performance.

[16]  Om Prakash Gangwal,et al.  Building Predictable Systems on Chip: An Analysis of Guaranteed Communication in the Aethereal Network on Chip , 2005 .

[17]  Sander Stuijk,et al.  SDF^3: SDF For Free , 2006, Sixth International Conference on Application of Concurrency to System Design (ACSD'06).

[18]  Alberto L. Sangiovanni-Vincentelli,et al.  Platform-Based Design and Software Design Methodology for Embedded Systems , 2001, IEEE Des. Test Comput..

[19]  Henk Corporaal,et al.  System-scenario-based design of dynamic embedded systems , 2009, TODE.

[20]  Edward A. Lee,et al.  Static Scheduling of Synchronous Data Flow Programs for Digital Signal Processing , 1989, IEEE Transactions on Computers.

[21]  Radu Marculescu,et al.  Energy- and performance-aware mapping for regular NoC architectures , 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[22]  Sander Stuijk,et al.  Throughput-Buffering Trade-Off Exploration for Cyclo-Static and Synchronous Dataflow Graphs , 2008, IEEE Transactions on Computers.

[23]  Sander Stuijk,et al.  Multiprocessor Resource Allocation for Throughput-Constrained Synchronous Dataflow Graphs , 2007, 2007 44th ACM/IEEE Design Automation Conference.

[24]  Shuvra S. Bhattacharyya,et al.  Embedded Multiprocessors: Scheduling and Synchronization , 2000 .