论文信息 - Inertial effect handling method for CMOS digital IC simulation

Inertial effect handling method for CMOS digital IC simulation

A method is presented for determining the occurrence of the inertial effect (pulse filtering) in CMOS digital logic gates to overcome the limitations of conventional approaches. It is based on accounting for individual input gate thresholds and a new scheduling mechanism, while maintaining compatibility with existing delay models.

Antonio J. Acosta | Manuel J. Bellido | Manuel Valencia | J. Juan-Chico

[1] John K. Ousterhout. A Switch-Level Timing Verifier for Digital MOS VLSI , 1985, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[2] Spiridon Nikolaidis,et al. Analytical transient response and propagation delay evaluation of the CMOS inverter for short-channel devices , 1998, IEEE J. Solid State Circuits.

[3] Stephen H. Unger. The essence of logic circuits , 1989 .

[4] D. Deschacht,et al. Input waveform slope effects in CMOS delays , 1990 .

[5] Trevor Mudge,et al. The impact of signal transition time on path delay computation , 1993 .

[6] Elmar U. K. Melcher,et al. Multiple input transitions in CMOS gates , 1992, Microprocess. Microprogramming.