Crosstalk analysis in nanometer technologies

Process variations have become a key concern of circuit designers because of their significant, yet hard to predict impact on performance and signal integrity of VLSI circuits. Statistical approaches have been suggested as the most effective substitute for corner-based approaches to deal with the variability of present process technology nodes. This paper introduces a statistical analysis of the crosstalk-aware delay of coupled interconnects considering process variations. The few existing works that have studied this problem suffer not only from shortcomings in their statistical models, but also from inaccurate crosstalk circuit models. We utilize an accurate distributed RC-p model of the interconnections to be able to model process variations close to reality. The considerable effect of correlation among the parameters of neighboring wire segments is also indicated. Statistical properties of the crosstalk-aware output delay are characterized and presented as closed-formed expressions. Monte Carlo Spice-based experimental results demonstrate the effectiveness of the proposed approach in accurately modeling the correlation-aware process variations and their impact on interconnect delay when crosstalk is present.

[1]  Andrew B. Kahng,et al.  Noise and delay uncertainty studies for coupled RC interconnects , 1999, Twelfth Annual IEEE International ASIC/SOC Conference (Cat. No.99TH8454).

[2]  P. Yang,et al.  Multilevel metal capacitance models for CAD design synthesis systems , 1992, IEEE Electron Device Letters.

[3]  Jason Cong,et al.  Improved crosstalk modeling for noise constrained interconnect optimization , 2001, ASP-DAC '01.

[4]  Shahin Nazarian,et al.  An empirical study of crosstalk in VDSM technologies , 2005, GLSVLSI '05.

[5]  Lawrence T. Pileggi,et al.  STAC: statistical timing analysis with correlation , 2004, Proceedings. 41st Design Automation Conference, 2004..

[6]  N. S. Nagaraj,et al.  BEOL variability and impact on RC extraction , 2005, Proceedings. 42nd Design Automation Conference, 2005..

[7]  Massoud Pedram,et al.  Analysis and reduction of capacitive coupling noise in high-speed VLSI circuits , 2001, Proceedings 2001 IEEE International Conference on Computer Design: VLSI in Computers and Processors. ICCD 2001.

[8]  Melvin A. Breuer,et al.  Analytical models for crosstalk excitation and propagation in VLSI circuits , 2002, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[9]  David Blaauw,et al.  Statistical modeling of cross-coupling effects in VLSI interconnects , 2005, Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005..

[10]  Rajendran Panda,et al.  Analysis of noise avoidance techniques in DSM interconnects using a complete crosstalk noise model , 2002, Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition.

[11]  David Blaauw,et al.  Statistical modeling of cross-coupling effects in VLSI interconnects , 2005, ASP-DAC '05.

[12]  Sani R. Nassif,et al.  Modeling interconnect variability using efficient parametric model order reduction , 2005, Design, Automation and Test in Europe.

[13]  Massoud Pedram,et al.  Capacitive coupling noise in high-speed VLSI circuits , 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[14]  Chandu Visweswariah,et al.  Death, taxes and failing chips , 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).

[15]  Guido Masera,et al.  A statistical model for estimating the effect of process variations on crosstalk noise , 2004, SLIP '04.

[16]  Lawrence T. Pileggi,et al.  PRIMA: passive reduced-order interconnect macromodeling algorithm , 1997, ICCAD 1997.

[17]  Sani R. Nassif,et al.  A methodology for modeling the effects of systematic within-die interconnect and device variation on circuit performance , 2000, Proceedings 37th Design Automation Conference.

[18]  Tom Chen,et al.  Statistical timing analysis of coupled interconnects using quadratic delay-change characteristics , 2004, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.