SwimmingLane: A composite approach to mitigate voltage droop effects in 3D power delivery network
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[1] Zheng Xu,et al. Decoupling capacitor modeling and characterization for power supply noise in 3D systems , 2012, 2012 SEMI Advanced Semiconductor Manufacturing Conference.
[2] Xiaowei Li,et al. Leveraging the core-level complementary effects of PVT variations to reduce timing emergencies in multi-core processors , 2010, ISCA '10.
[3] Milo M. K. Martin,et al. Multifacet's general execution-driven multiprocessor simulator (GEMS) toolset , 2005, CARN.
[4] Yu Hu,et al. Orchestrator: A low-cost solution to reduce voltage emergencies for multi-threaded applications , 2013, 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE).
[5] David M. Brooks,et al. Resilient Architectures via Collaborative Design: Maximizing Commodity Processor Performance in the Presence of Variations , 2011, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[6] Sung Kyu Lim,et al. Distributed TSV Topology for 3-D Power-Supply Networks , 2012, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[7] Meeta Sharma Gupta,et al. Towards a software approach to mitigate voltage emergencies , 2007, Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07).
[8] John Keane,et al. A multi-story power delivery technique for 3D integrated circuits , 2008, Proceeding of the 13th international symposium on Low power electronics and design (ISLPED '08).
[9] Meeta Sharma Gupta,et al. Understanding Voltage Variations in Chip Multiprocessors using a Distributed Power-Delivery Network , 2007, 2007 Design, Automation & Test in Europe Conference & Exhibition.
[10] Yu Wang,et al. Thermal-aware power network design for IR drop reduction in 3D ICs , 2012, 17th Asia and South Pacific Design Automation Conference.
[11] Nam Sung Kim,et al. Energy-Efficient and Metastability-Immune Timing-Error Detection and Instruction-Replay-Based Recovery Circuits for Dynamic-Variation Tolerance , 2008, 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.
[12] Gang Huang,et al. Power Delivery for 3D Chip Stacks: Physical Modeling and Design Implication , 2007, 2007 IEEE Electrical Performance of Electronic Packaging.
[13] Soha Hassoun,et al. Power Delivery Design for 3-D ICs Using Different Through-Silicon Via (TSV) Technologies , 2011, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[14] Joungho Kim,et al. Slow wave and dielectric quasi-TEM modes of Metal-Insulator-Semiconductor (MIS) structure Through Silicon Via (TSV) in signal propagation and power delivery in 3D chip package , 2010, 2010 Proceedings 60th Electronic Components and Technology Conference (ECTC).
[15] David Ayers,et al. Chip-package-board co-design of a 45nm 8-core enterprise Xeon processor , 2010, 2010 Proceedings 60th Electronic Components and Technology Conference (ECTC).
[16] Gang Huang,et al. Power Delivery for 3-D Chip Stacks: Physical Modeling and Design Implication , 2012, IEEE Transactions on Components, Packaging and Manufacturing Technology.
[17] Sung Kyu Lim,et al. Power-supply-network design in 3D integrated systems , 2011, 2011 12th International Symposium on Quality Electronic Design.
[18] Anoop Gupta,et al. The SPLASH-2 programs: characterization and methodological considerations , 1995, ISCA.
[19] Margaret Martonosi,et al. Wattch: a framework for architectural-level power analysis and optimizations , 2000, Proceedings of 27th International Symposium on Computer Architecture (IEEE Cat. No.RS00201).
[20] Soraya Ghiasi,et al. A Distributed Critical-Path Timing Monitor for a 65nm High-Performance Microprocessor , 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.
[21] Sung Kyu Lim,et al. A fine-grained co-simulation methodology for IR-drop noise in silicon interposer and TSV-based 3D IC , 2011, 2011 IEEE 20th Conference on Electrical Performance of Electronic Packaging and Systems.
[22] Bishop Brock,et al. Active management of timing guardband to save energy in POWER7 , 2011, 2011 44th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).
[23] Michael D. Smith,et al. Voltage Smoothing: Characterizing and Mitigating Voltage Noise in Production Processors via Software-Guided Thread Scheduling , 2010, 2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture.
[24] GABRIEL H. LOH,et al. 3D Stacked Microprocessor: Are We There Yet? , 2010, IEEE Micro.
[25] Jun Yang,et al. Thermal-Aware Task Scheduling for 3D Multicore Processors , 2010, IEEE Transactions on Parallel and Distributed Systems.