Static and Dynamic Mapping Heuristics for Multiprocessor Systems-on-Chip

In the Algerian republic, scientific and intensive computing are a priority in the strategy of the scientific research between 2013 and 2017. To put into practice this strategy, 32 nodes of high-performance computing were installed in Algeria in particular in the University of Oran. The work that we present in this chapter is our contribution to this priority in the area of intensive embedded computing: static and dynamic mapping heuristics for single chip systems.

[1]  Gerard J. M. Smit,et al.  Mapping streaming applications on a reconfigurable MPSoC platform at run-time , 2007, 2007 International Symposium on System-on-Chip.

[2]  Radu Marculescu,et al.  User-Aware Dynamic Task Allocation in Networks-on-Chip , 2008, 2008 Design, Automation and Test in Europe.

[3]  Luca Benini,et al.  Allocation, Scheduling and Voltage Scaling on Energy Aware MPSoCs , 2006, CPAIOR.

[4]  Hugo Jair Escalante,et al.  Particle Swarm Model Selection , 2009, J. Mach. Learn. Res..

[5]  Pierre Boulet,et al.  Multi-objective Mapping for NoC Architectures , 2007, J. Digit. Inf. Manag..

[6]  Gerard J. M. Smit,et al.  Run-time Spatial Mapping of Streaming Applications to a Heterogeneous Multi-Processor System-on-Chip (MPSOC) , 2007, 2008 Design, Automation and Test in Europe.

[7]  Alexander Hall,et al.  Energy efficient application mapping to NoC processing elements operating at multiple voltage levels , 2009, 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip.

[8]  Radu Marculescu,et al.  Incremental run-time application mapping for homogeneous NoCs with multiple voltage levels , 2007, 2007 5th IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS).

[9]  Ahmad Khademzadeh,et al.  Crinkle: A heuristic mapping algorithm for network on chip , 2009, IEICE Electron. Express.

[10]  Fernando Gehm Moraes,et al.  Dynamic Task Mapping for MPSoCs , 2010, IEEE Design & Test of Computers.

[11]  Amit Kumar Singh,et al.  Efficient Heuristics for Minimizing Communication Overhead in NoC-based Heterogeneous MPSoC Platforms , 2009, 2009 IEEE/IFIP International Symposium on Rapid System Prototyping.

[12]  Luca Benini,et al.  Networks on Chips : A New SoC Paradigm , 2022 .

[13]  Alexandre M. Amory,et al.  Multi-task dynamic mapping onto NoC-based MPSoCs , 2011, SBCCI '11.

[14]  Tobias Bjerregaard,et al.  A survey of research and practices of Network-on-chip , 2006, CSUR.

[15]  Vincenzo Catania,et al.  A Multi-objective Genetic Approach to Mapping Problem on Network-on-Chip , 2006, J. Univers. Comput. Sci..

[16]  Ney Laert Vilar Calazans,et al.  Evaluation of static and dynamic task mapping algorithms in NoC-based MPSoCs , 2009, 2009 International Symposium on System-on-Chip.

[17]  G.J.M. Smit,et al.  Run-time Mapping of Applications to a Heterogeneous SoC , 2005, 2005 International Symposium on System-on-Chip.

[18]  Xiaobo Sharon Hu,et al.  Task scheduling and voltage selection for energy minimization , 2002, DAC '02.

[19]  Jörg Henkel,et al.  ADAM: Run-time agent-based distributed application mapping for on-chip communication , 2008, 2008 45th ACM/IEEE Design Automation Conference.

[20]  Yingtao Jiang,et al.  Power-Aware Mapping for Network-on-Chip Architectures under Bandwidth and Latency Constraints , 2009, 2009 Fourth International Conference on Embedded and Multimedia Computing.

[21]  Edoardo Amaldi,et al.  Optimization models and methods for planning wireless mesh networks , 2008, Comput. Networks.

[22]  Ahmad Khademzadeh,et al.  DSM: A Heuristic Dynamic Spiral Mapping algorithm for network on chip , 2008, IEICE Electron. Express.

[23]  Pierre Boulet,et al.  An Hybrid algorithm for Mapping on NoC Architectures , 2008 .

[24]  Lothar Thiele,et al.  Dynamic and adaptive allocation of applications on MPSoC platforms , 2010, 2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC).

[25]  E. Carvalho,et al.  Congestion-aware task mapping in heterogeneous MPSoCs , 2008, 2008 International Symposium on System-on-Chip.

[26]  Amit Kumar Singh,et al.  Communication-aware heuristics for run-time task mapping on NoC-based MPSoC platforms , 2010, J. Syst. Archit..

[27]  Dongkun Shin,et al.  Power-aware communication optimization for networks-on-chips with voltage scalable links , 2004, International Conference on Hardware/Software Codesign and System Synthesis, 2004. CODES + ISSS 2004..