The over-bump applied resin wafer-level underfill process: Process, material and reliability
暂无分享,去创建一个
Michael Gaynes | Claudius Feger | Mark Francis | N. LaBianca | C. Feger | M. Gaynes | S. Steen | Nancy LaBianca | Steven Steen | Zhen Liu | Raj Peddi | R. Peddi | Zhen Liu | M. Francis
[1] The effect of filler on the solder connection for no-flow underfill , 2006, 56th Electronic Components and Technology Conference 2006.
[2] David A. Hutt,et al. Evaluation of pre‐deposited (no‐flow) underfill for flip chip and CSP assembly , 1999 .
[3] Ching-Ping Wong,et al. High performance no-flow underfills for low-cost flip-chip applications: material characterization , 1998 .
[4] Recent advances on a wafer-level flip chip packaging process , 2000, 2000 Proceedings. 50th Electronic Components and Technology Conference (Cat. No.00CH37070).
[5] D. Baldwin,et al. No-flow underfill process optimization for high yield and reliability in flip chip assembly , 2002, 2002 Proceedings. 8th International Advanced Packaging Materials Symposium (Cat. No.02TH8617).
[6] Luke Garner,et al. Finding Solutions to the Challenges in Package Interconnect Reliability , 2005 .
[7] Tie Wang,et al. Flip-chip assembly development via modified reflowable underfill process , 2001, 2001 Proceedings. 51st Electronic Components and Technology Conference (Cat. No.01CH37220).
[8] C. Wong,et al. Development of the wafer level compressive-flow underfill process and its required materials , 1999, 1999 Proceedings. 49th Electronic Components and Technology Conference (Cat. No.99CH36299).
[9] Ching-ping Wong,et al. Flip Chip Underfill: Materials, Process, and Reliability , 2009 .